include/llvm/Support/X86DisassemblerDecoderCommon.h

   1 //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file is part of the X86 Disassembler.
  10 // It contains common definitions used by both the disassembler and the table
  11 //  generator.
  12 // Documentation for the disassembler can be found in X86Disassembler.h.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODERCOMMON_H
  17 #define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODERCOMMON_H
  18
  19 #include "llvm/Support/DataTypes.h"
  20
  21 namespace llvm {
  22 namespace X86Disassembler {
  23
  24 #define INSTRUCTIONS_SYM  x86DisassemblerInstrSpecifiers
  25 #define CONTEXTS_SYM      x86DisassemblerContexts
  26 #define ONEBYTE_SYM       x86DisassemblerOneByteOpcodes
  27 #define TWOBYTE_SYM       x86DisassemblerTwoByteOpcodes
  28 #define THREEBYTE38_SYM   x86DisassemblerThreeByte38Opcodes
  29 #define THREEBYTE3A_SYM   x86DisassemblerThreeByte3AOpcodes
  30 #define XOP8_MAP_SYM      x86DisassemblerXOP8Opcodes
  31 #define XOP9_MAP_SYM      x86DisassemblerXOP9Opcodes
  32 #define XOPA_MAP_SYM      x86DisassemblerXOPAOpcodes
  33 #define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes
  34
  35 #define INSTRUCTIONS_STR  "x86DisassemblerInstrSpecifiers"
  36 #define CONTEXTS_STR      "x86DisassemblerContexts"
  37 #define ONEBYTE_STR       "x86DisassemblerOneByteOpcodes"
  38 #define TWOBYTE_STR       "x86DisassemblerTwoByteOpcodes"
  39 #define THREEBYTE38_STR   "x86DisassemblerThreeByte38Opcodes"
  40 #define THREEBYTE3A_STR   "x86DisassemblerThreeByte3AOpcodes"
  41 #define XOP8_MAP_STR      "x86DisassemblerXOP8Opcodes"
  42 #define XOP9_MAP_STR      "x86DisassemblerXOP9Opcodes"
  43 #define XOPA_MAP_STR      "x86DisassemblerXOPAOpcodes"
  44 #define THREEDNOW_MAP_STR "x86Disassembler3DNowOpcodes"
  45
  46 // Attributes of an instruction that must be known before the opcode can be
  47 // processed correctly.  Most of these indicate the presence of particular
  48 // prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
  49 enum attributeBits {
  50   ATTR_NONE   = 0x00,
  51   ATTR_64BIT  = 0x1 << 0,
  52   ATTR_XS     = 0x1 << 1,
  53   ATTR_XD     = 0x1 << 2,
  54   ATTR_REXW   = 0x1 << 3,
  55   ATTR_OPSIZE = 0x1 << 4,
  56   ATTR_ADSIZE = 0x1 << 5,
  57   ATTR_VEX    = 0x1 << 6,
  58   ATTR_VEXL   = 0x1 << 7,
  59   ATTR_EVEX   = 0x1 << 8,
  60   ATTR_EVEXL2 = 0x1 << 9,
  61   ATTR_EVEXK  = 0x1 << 10,
  62   ATTR_EVEXKZ = 0x1 << 11,
  63   ATTR_EVEXB  = 0x1 << 12,
  64   ATTR_max    = 0x1 << 13,
  65 };
  66
  67 // Combinations of the above attributes that are relevant to instruction
  68 // decode. Although other combinations are possible, they can be reduced to
  69 // these without affecting the ultimately decoded instruction.
  70
  71 //           Class name           Rank  Rationale for rank assignment
  72 #define INSTRUCTION_CONTEXTS                                                   \
  73   ENUM_ENTRY(IC,                    0,  "says nothing about the instruction")  \
  74   ENUM_ENTRY(IC_64BIT,              1,  "says the instruction applies in "     \
  75                                         "64-bit mode but no more")             \
  76   ENUM_ENTRY(IC_OPSIZE,             3,  "requires an OPSIZE prefix, so "       \
  77                                         "operands change width")               \
  78   ENUM_ENTRY(IC_ADSIZE,             3,  "requires an ADSIZE prefix, so "       \
  79                                         "operands change width")               \
  80   ENUM_ENTRY(IC_OPSIZE_ADSIZE,      4,  "requires ADSIZE and OPSIZE prefixes") \
  81   ENUM_ENTRY(IC_XD,                 2,  "may say something about the opcode "  \
  82                                         "but not the operands")                \
  83   ENUM_ENTRY(IC_XS,                 2,  "may say something about the opcode "  \
  84                                         "but not the operands")                \
  85   ENUM_ENTRY(IC_XD_OPSIZE,          3,  "requires an OPSIZE prefix, so "       \
  86                                         "operands change width")               \
  87   ENUM_ENTRY(IC_XS_OPSIZE,          3,  "requires an OPSIZE prefix, so "       \
  88                                         "operands change width")               \
  89   ENUM_ENTRY(IC_XD_ADSIZE,          3,  "requires an ADSIZE prefix, so "       \
  90                                         "operands change width")               \
  91   ENUM_ENTRY(IC_XS_ADSIZE,          3,  "requires an ADSIZE prefix, so "       \
  92                                         "operands change width")               \
  93   ENUM_ENTRY(IC_64BIT_REXW,         5,  "requires a REX.W prefix, so operands "\
  94                                         "change width; overrides IC_OPSIZE")   \
  95   ENUM_ENTRY(IC_64BIT_REXW_ADSIZE,  6,  "requires a REX.W prefix and 0x67 "    \
  96                                         "prefix")                              \
  97   ENUM_ENTRY(IC_64BIT_OPSIZE,       3,  "Just as meaningful as IC_OPSIZE")     \
  98   ENUM_ENTRY(IC_64BIT_ADSIZE,       3,  "Just as meaningful as IC_ADSIZE")     \
  99   ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/"     \
 100                                         "IC_ADSIZE")                           \
 101   ENUM_ENTRY(IC_64BIT_XD,           6,  "XD instructions are SSE; REX.W is "   \
 102                                         "secondary")                           \
 103   ENUM_ENTRY(IC_64BIT_XS,           6,  "Just as meaningful as IC_64BIT_XD")   \
 104   ENUM_ENTRY(IC_64BIT_XD_OPSIZE,    3,  "Just as meaningful as IC_XD_OPSIZE")  \
 105   ENUM_ENTRY(IC_64BIT_XS_OPSIZE,    3,  "Just as meaningful as IC_XS_OPSIZE")  \
 106   ENUM_ENTRY(IC_64BIT_XD_ADSIZE,    3,  "Just as meaningful as IC_XD_ADSIZE")  \
 107   ENUM_ENTRY(IC_64BIT_XS_ADSIZE,    3,  "Just as meaningful as IC_XS_ADSIZE")  \
 108   ENUM_ENTRY(IC_64BIT_REXW_XS,      7,  "OPSIZE could mean a different "       \
 109                                         "opcode")                              \
 110   ENUM_ENTRY(IC_64BIT_REXW_XD,      7,  "Just as meaningful as "               \
 111                                         "IC_64BIT_REXW_XS")                    \
 112   ENUM_ENTRY(IC_64BIT_REXW_OPSIZE,  8,  "The Dynamic Duo!  Prefer over all "   \
 113                                         "else because this changes most "      \
 114                                         "operands' meaning")                   \
 115   ENUM_ENTRY(IC_VEX,                1,  "requires a VEX prefix")               \
 116   ENUM_ENTRY(IC_VEX_XS,             2,  "requires VEX and the XS prefix")      \
 117   ENUM_ENTRY(IC_VEX_XD,             2,  "requires VEX and the XD prefix")      \
 118   ENUM_ENTRY(IC_VEX_OPSIZE,         2,  "requires VEX and the OpSize prefix")  \
 119   ENUM_ENTRY(IC_VEX_W,              3,  "requires VEX and the W prefix")       \
 120   ENUM_ENTRY(IC_VEX_W_XS,           4,  "requires VEX, W, and XS prefix")      \
 121   ENUM_ENTRY(IC_VEX_W_XD,           4,  "requires VEX, W, and XD prefix")      \
 122   ENUM_ENTRY(IC_VEX_W_OPSIZE,       4,  "requires VEX, W, and OpSize")         \
 123   ENUM_ENTRY(IC_VEX_L,              3,  "requires VEX and the L prefix")       \
 124   ENUM_ENTRY(IC_VEX_L_XS,           4,  "requires VEX and the L and XS prefix")\
 125   ENUM_ENTRY(IC_VEX_L_XD,           4,  "requires VEX and the L and XD prefix")\
 126   ENUM_ENTRY(IC_VEX_L_OPSIZE,       4,  "requires VEX, L, and OpSize")         \
 127   ENUM_ENTRY(IC_VEX_L_W,            4,  "requires VEX, L and W")               \
 128   ENUM_ENTRY(IC_VEX_L_W_XS,         5,  "requires VEX, L, W and XS prefix")    \
 129   ENUM_ENTRY(IC_VEX_L_W_XD,         5,  "requires VEX, L, W and XD prefix")    \
 130   ENUM_ENTRY(IC_VEX_L_W_OPSIZE,     5,  "requires VEX, L, W and OpSize")       \
 131   ENUM_ENTRY(IC_EVEX,               1,  "requires an EVEX prefix")             \
 132   ENUM_ENTRY(IC_EVEX_XS,            2,  "requires EVEX and the XS prefix")     \
 133   ENUM_ENTRY(IC_EVEX_XD,            2,  "requires EVEX and the XD prefix")     \
 134   ENUM_ENTRY(IC_EVEX_OPSIZE,        2,  "requires EVEX and the OpSize prefix") \
 135   ENUM_ENTRY(IC_EVEX_W,             3,  "requires EVEX and the W prefix")      \
 136   ENUM_ENTRY(IC_EVEX_W_XS,          4,  "requires EVEX, W, and XS prefix")     \
 137   ENUM_ENTRY(IC_EVEX_W_XD,          4,  "requires EVEX, W, and XD prefix")     \
 138   ENUM_ENTRY(IC_EVEX_W_OPSIZE,      4,  "requires EVEX, W, and OpSize")        \
 139   ENUM_ENTRY(IC_EVEX_L,             3,  "requires EVEX and the L prefix")       \
 140   ENUM_ENTRY(IC_EVEX_L_XS,          4,  "requires EVEX and the L and XS prefix")\
 141   ENUM_ENTRY(IC_EVEX_L_XD,          4,  "requires EVEX and the L and XD prefix")\
 142   ENUM_ENTRY(IC_EVEX_L_OPSIZE,      4,  "requires EVEX, L, and OpSize")         \
 143   ENUM_ENTRY(IC_EVEX_L_W,           3,  "requires EVEX, L and W")               \
 144   ENUM_ENTRY(IC_EVEX_L_W_XS,        4,  "requires EVEX, L, W and XS prefix")    \
 145   ENUM_ENTRY(IC_EVEX_L_W_XD,        4,  "requires EVEX, L, W and XD prefix")    \
 146   ENUM_ENTRY(IC_EVEX_L_W_OPSIZE,    4,  "requires EVEX, L, W and OpSize")       \
 147   ENUM_ENTRY(IC_EVEX_L2,            3,  "requires EVEX and the L2 prefix")       \
 148   ENUM_ENTRY(IC_EVEX_L2_XS,         4,  "requires EVEX and the L2 and XS prefix")\
 149   ENUM_ENTRY(IC_EVEX_L2_XD,         4,  "requires EVEX and the L2 and XD prefix")\
 150   ENUM_ENTRY(IC_EVEX_L2_OPSIZE,     4,  "requires EVEX, L2, and OpSize")         \
 151   ENUM_ENTRY(IC_EVEX_L2_W,          3,  "requires EVEX, L2 and W")               \
 152   ENUM_ENTRY(IC_EVEX_L2_W_XS,       4,  "requires EVEX, L2, W and XS prefix")    \
 153   ENUM_ENTRY(IC_EVEX_L2_W_XD,       4,  "requires EVEX, L2, W and XD prefix")    \
 154   ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE,   4,  "requires EVEX, L2, W and OpSize")       \
 155   ENUM_ENTRY(IC_EVEX_K,             1,  "requires an EVEX_K prefix")             \
 156   ENUM_ENTRY(IC_EVEX_XS_K,          2,  "requires EVEX_K and the XS prefix")     \
 157   ENUM_ENTRY(IC_EVEX_XD_K,          2,  "requires EVEX_K and the XD prefix")     \
 158   ENUM_ENTRY(IC_EVEX_OPSIZE_K,      2,  "requires EVEX_K and the OpSize prefix") \
 159   ENUM_ENTRY(IC_EVEX_W_K,           3,  "requires EVEX_K and the W prefix")      \
 160   ENUM_ENTRY(IC_EVEX_W_XS_K,        4,  "requires EVEX_K, W, and XS prefix")     \
 161   ENUM_ENTRY(IC_EVEX_W_XD_K,        4,  "requires EVEX_K, W, and XD prefix")     \
 162   ENUM_ENTRY(IC_EVEX_W_OPSIZE_K,    4,  "requires EVEX_K, W, and OpSize")        \
 163   ENUM_ENTRY(IC_EVEX_L_K,           3,  "requires EVEX_K and the L prefix")       \
 164   ENUM_ENTRY(IC_EVEX_L_XS_K,        4,  "requires EVEX_K and the L and XS prefix")\
 165   ENUM_ENTRY(IC_EVEX_L_XD_K,        4,  "requires EVEX_K and the L and XD prefix")\
 166   ENUM_ENTRY(IC_EVEX_L_OPSIZE_K,    4,  "requires EVEX_K, L, and OpSize")         \
 167   ENUM_ENTRY(IC_EVEX_L_W_K,         3,  "requires EVEX_K, L and W")               \
 168   ENUM_ENTRY(IC_EVEX_L_W_XS_K,      4,  "requires EVEX_K, L, W and XS prefix")    \
 169   ENUM_ENTRY(IC_EVEX_L_W_XD_K,      4,  "requires EVEX_K, L, W and XD prefix")    \
 170   ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K,  4,  "requires EVEX_K, L, W and OpSize")       \
 171   ENUM_ENTRY(IC_EVEX_L2_K,          3,  "requires EVEX_K and the L2 prefix")       \
 172   ENUM_ENTRY(IC_EVEX_L2_XS_K,       4,  "requires EVEX_K and the L2 and XS prefix")\
 173   ENUM_ENTRY(IC_EVEX_L2_XD_K,       4,  "requires EVEX_K and the L2 and XD prefix")\
 174   ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K,   4,  "requires EVEX_K, L2, and OpSize")         \
 175   ENUM_ENTRY(IC_EVEX_L2_W_K,        3,  "requires EVEX_K, L2 and W")               \
 176   ENUM_ENTRY(IC_EVEX_L2_W_XS_K,     4,  "requires EVEX_K, L2, W and XS prefix")    \
 177   ENUM_ENTRY(IC_EVEX_L2_W_XD_K,     4,  "requires EVEX_K, L2, W and XD prefix")    \
 178   ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4,  "requires EVEX_K, L2, W and OpSize")     \
 179   ENUM_ENTRY(IC_EVEX_B,             1,  "requires an EVEX_B prefix")             \
 180   ENUM_ENTRY(IC_EVEX_XS_B,          2,  "requires EVEX_B and the XS prefix")     \
 181   ENUM_ENTRY(IC_EVEX_XD_B,          2,  "requires EVEX_B and the XD prefix")     \
 182   ENUM_ENTRY(IC_EVEX_OPSIZE_B,      2,  "requires EVEX_B and the OpSize prefix") \
 183   ENUM_ENTRY(IC_EVEX_W_B,           3,  "requires EVEX_B and the W prefix")      \
 184   ENUM_ENTRY(IC_EVEX_W_XS_B,        4,  "requires EVEX_B, W, and XS prefix")     \
 185   ENUM_ENTRY(IC_EVEX_W_XD_B,        4,  "requires EVEX_B, W, and XD prefix")     \
 186   ENUM_ENTRY(IC_EVEX_W_OPSIZE_B,    4,  "requires EVEX_B, W, and OpSize")        \
 187   ENUM_ENTRY(IC_EVEX_L_B,           3,  "requires EVEX_B and the L prefix")       \
 188   ENUM_ENTRY(IC_EVEX_L_XS_B,        4,  "requires EVEX_B and the L and XS prefix")\
 189   ENUM_ENTRY(IC_EVEX_L_XD_B,        4,  "requires EVEX_B and the L and XD prefix")\
 190   ENUM_ENTRY(IC_EVEX_L_OPSIZE_B,    4,  "requires EVEX_B, L, and OpSize")         \
 191   ENUM_ENTRY(IC_EVEX_L_W_B,         3,  "requires EVEX_B, L and W")               \
 192   ENUM_ENTRY(IC_EVEX_L_W_XS_B,      4,  "requires EVEX_B, L, W and XS prefix")    \
 193   ENUM_ENTRY(IC_EVEX_L_W_XD_B,      4,  "requires EVEX_B, L, W and XD prefix")    \
 194   ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B,  4,  "requires EVEX_B, L, W and OpSize")       \
 195   ENUM_ENTRY(IC_EVEX_L2_B,          3,  "requires EVEX_B and the L2 prefix")       \
 196   ENUM_ENTRY(IC_EVEX_L2_XS_B,       4,  "requires EVEX_B and the L2 and XS prefix")\
 197   ENUM_ENTRY(IC_EVEX_L2_XD_B,       4,  "requires EVEX_B and the L2 and XD prefix")\
 198   ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B,   4,  "requires EVEX_B, L2, and OpSize")         \
 199   ENUM_ENTRY(IC_EVEX_L2_W_B,        3,  "requires EVEX_B, L2 and W")               \
 200   ENUM_ENTRY(IC_EVEX_L2_W_XS_B,     4,  "requires EVEX_B, L2, W and XS prefix")    \
 201   ENUM_ENTRY(IC_EVEX_L2_W_XD_B,     4,  "requires EVEX_B, L2, W and XD prefix")    \
 202   ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4,  "requires EVEX_B, L2, W and OpSize")       \
 203   ENUM_ENTRY(IC_EVEX_K_B,           1,  "requires EVEX_B and EVEX_K prefix")             \
 204   ENUM_ENTRY(IC_EVEX_XS_K_B,        2,  "requires EVEX_B, EVEX_K and the XS prefix")     \
 205   ENUM_ENTRY(IC_EVEX_XD_K_B,        2,  "requires EVEX_B, EVEX_K and the XD prefix")     \
 206   ENUM_ENTRY(IC_EVEX_OPSIZE_K_B,    2,  "requires EVEX_B, EVEX_K and the OpSize prefix") \
 207   ENUM_ENTRY(IC_EVEX_W_K_B,         3,  "requires EVEX_B, EVEX_K and the W prefix")      \
 208   ENUM_ENTRY(IC_EVEX_W_XS_K_B,      4,  "requires EVEX_B, EVEX_K, W, and XS prefix")     \
 209   ENUM_ENTRY(IC_EVEX_W_XD_K_B,      4,  "requires EVEX_B, EVEX_K, W, and XD prefix")     \
 210   ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B,  4,  "requires EVEX_B, EVEX_K, W, and OpSize")        \
 211   ENUM_ENTRY(IC_EVEX_L_K_B,         3,  "requires EVEX_B, EVEX_K and the L prefix")       \
 212   ENUM_ENTRY(IC_EVEX_L_XS_K_B,      4,  "requires EVEX_B, EVEX_K and the L and XS prefix")\
 213   ENUM_ENTRY(IC_EVEX_L_XD_K_B,      4,  "requires EVEX_B, EVEX_K and the L and XD prefix")\
 214   ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B,  4,  "requires EVEX_B, EVEX_K, L, and OpSize")         \
 215   ENUM_ENTRY(IC_EVEX_L_W_K_B,       3,  "requires EVEX_B, EVEX_K, L and W")               \
 216   ENUM_ENTRY(IC_EVEX_L_W_XS_K_B,    4,  "requires EVEX_B, EVEX_K, L, W and XS prefix")    \
 217   ENUM_ENTRY(IC_EVEX_L_W_XD_K_B,    4,  "requires EVEX_B, EVEX_K, L, W and XD prefix")    \
 218   ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4,  "requires EVEX_B, EVEX_K, L, W and OpSize")       \
 219   ENUM_ENTRY(IC_EVEX_L2_K_B,        3,  "requires EVEX_B, EVEX_K and the L2 prefix")       \
 220   ENUM_ENTRY(IC_EVEX_L2_XS_K_B,     4,  "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
 221   ENUM_ENTRY(IC_EVEX_L2_XD_K_B,     4,  "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
 222   ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4,  "requires EVEX_B, EVEX_K, L2, and OpSize")         \
 223   ENUM_ENTRY(IC_EVEX_L2_W_K_B,      3,  "requires EVEX_B, EVEX_K, L2 and W")               \
 224   ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B,   4,  "requires EVEX_B, EVEX_K, L2, W and XS prefix")    \
 225   ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B,   4,  "requires EVEX_B, EVEX_K, L2, W and XD prefix")    \
 226   ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4,  "requires EVEX_B, EVEX_K, L2, W and OpSize")       \
 227   ENUM_ENTRY(IC_EVEX_KZ_B,           1,  "requires EVEX_B and EVEX_KZ prefix")             \
 228   ENUM_ENTRY(IC_EVEX_XS_KZ_B,        2,  "requires EVEX_B, EVEX_KZ and the XS prefix")     \
 229   ENUM_ENTRY(IC_EVEX_XD_KZ_B,        2,  "requires EVEX_B, EVEX_KZ and the XD prefix")     \
 230   ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B,    2,  "requires EVEX_B, EVEX_KZ and the OpSize prefix") \
 231   ENUM_ENTRY(IC_EVEX_W_KZ_B,         3,  "requires EVEX_B, EVEX_KZ and the W prefix")      \
 232   ENUM_ENTRY(IC_EVEX_W_XS_KZ_B,      4,  "requires EVEX_B, EVEX_KZ, W, and XS prefix")     \
 233   ENUM_ENTRY(IC_EVEX_W_XD_KZ_B,      4,  "requires EVEX_B, EVEX_KZ, W, and XD prefix")     \
 234   ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B,  4,  "requires EVEX_B, EVEX_KZ, W, and OpSize")        \
 235   ENUM_ENTRY(IC_EVEX_L_KZ_B,           3,  "requires EVEX_B, EVEX_KZ and the L prefix")       \
 236   ENUM_ENTRY(IC_EVEX_L_XS_KZ_B,        4,  "requires EVEX_B, EVEX_KZ and the L and XS prefix")\
 237   ENUM_ENTRY(IC_EVEX_L_XD_KZ_B,        4,  "requires EVEX_B, EVEX_KZ and the L and XD prefix")\
 238   ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B,    4,  "requires EVEX_B, EVEX_KZ, L, and OpSize")         \
 239   ENUM_ENTRY(IC_EVEX_L_W_KZ_B,         3,  "requires EVEX_B, EVEX_KZ, L and W")               \
 240   ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B,      4,  "requires EVEX_B, EVEX_KZ, L, W and XS prefix")    \
 241   ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B,      4,  "requires EVEX_B, EVEX_KZ, L, W and XD prefix")    \
 242   ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B,  4,  "requires EVEX_B, EVEX_KZ, L, W and OpSize")       \
 243   ENUM_ENTRY(IC_EVEX_L2_KZ_B,          3,  "requires EVEX_B, EVEX_KZ and the L2 prefix")       \
 244   ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B,       4,  "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\
 245   ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B,       4,  "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\
 246   ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B,   4,  "requires EVEX_B, EVEX_KZ, L2, and OpSize")         \
 247   ENUM_ENTRY(IC_EVEX_L2_W_KZ_B,        3,  "requires EVEX_B, EVEX_KZ, L2 and W")               \
 248   ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B,     4,  "requires EVEX_B, EVEX_KZ, L2, W and XS prefix")    \
 249   ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B,     4,  "requires EVEX_B, EVEX_KZ, L2, W and XD prefix")    \
 250   ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4,  "requires EVEX_B, EVEX_KZ, L2, W and OpSize")       \
 251   ENUM_ENTRY(IC_EVEX_KZ,             1,  "requires an EVEX_KZ prefix")             \
 252   ENUM_ENTRY(IC_EVEX_XS_KZ,          2,  "requires EVEX_KZ and the XS prefix")     \
 253   ENUM_ENTRY(IC_EVEX_XD_KZ,          2,  "requires EVEX_KZ and the XD prefix")     \
 254   ENUM_ENTRY(IC_EVEX_OPSIZE_KZ,      2,  "requires EVEX_KZ and the OpSize prefix") \
 255   ENUM_ENTRY(IC_EVEX_W_KZ,           3,  "requires EVEX_KZ and the W prefix")      \
 256   ENUM_ENTRY(IC_EVEX_W_XS_KZ,        4,  "requires EVEX_KZ, W, and XS prefix")     \
 257   ENUM_ENTRY(IC_EVEX_W_XD_KZ,        4,  "requires EVEX_KZ, W, and XD prefix")     \
 258   ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ,    4,  "requires EVEX_KZ, W, and OpSize")        \
 259   ENUM_ENTRY(IC_EVEX_L_KZ,           3,  "requires EVEX_KZ and the L prefix")       \
 260   ENUM_ENTRY(IC_EVEX_L_XS_KZ,        4,  "requires EVEX_KZ and the L and XS prefix")\
 261   ENUM_ENTRY(IC_EVEX_L_XD_KZ,        4,  "requires EVEX_KZ and the L and XD prefix")\
 262   ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ,    4,  "requires EVEX_KZ, L, and OpSize")         \
 263   ENUM_ENTRY(IC_EVEX_L_W_KZ,         3,  "requires EVEX_KZ, L and W")               \
 264   ENUM_ENTRY(IC_EVEX_L_W_XS_KZ,      4,  "requires EVEX_KZ, L, W and XS prefix")    \
 265   ENUM_ENTRY(IC_EVEX_L_W_XD_KZ,      4,  "requires EVEX_KZ, L, W and XD prefix")    \
 266   ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ,  4,  "requires EVEX_KZ, L, W and OpSize")       \
 267   ENUM_ENTRY(IC_EVEX_L2_KZ,          3,  "requires EVEX_KZ and the L2 prefix")       \
 268   ENUM_ENTRY(IC_EVEX_L2_XS_KZ,       4,  "requires EVEX_KZ and the L2 and XS prefix")\
 269   ENUM_ENTRY(IC_EVEX_L2_XD_KZ,       4,  "requires EVEX_KZ and the L2 and XD prefix")\
 270   ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ,   4,  "requires EVEX_KZ, L2, and OpSize")         \
 271   ENUM_ENTRY(IC_EVEX_L2_W_KZ,        3,  "requires EVEX_KZ, L2 and W")               \
 272   ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ,     4,  "requires EVEX_KZ, L2, W and XS prefix")    \
 273   ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ,     4,  "requires EVEX_KZ, L2, W and XD prefix")    \
 274   ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4,  "requires EVEX_KZ, L2, W and OpSize")
 275
 276 #define ENUM_ENTRY(n, r, d) n,
 277 enum InstructionContext {
 278   INSTRUCTION_CONTEXTS
 279   IC_max
 280 };
 281 #undef ENUM_ENTRY
 282
 283 // Opcode types, which determine which decode table to use, both in the Intel
 284 // manual and also for the decoder.
 285 enum OpcodeType {
 286   ONEBYTE       = 0,
 287   TWOBYTE       = 1,
 288   THREEBYTE_38  = 2,
 289   THREEBYTE_3A  = 3,
 290   XOP8_MAP      = 4,
 291   XOP9_MAP      = 5,
 292   XOPA_MAP      = 6,
 293   THREEDNOW_MAP = 7
 294 };
 295
 296 // The following structs are used for the hierarchical decode table.  After
 297 // determining the instruction's class (i.e., which IC_* constant applies to
 298 // it), the decoder reads the opcode.  Some instructions require specific
 299 // values of the ModR/M byte, so the ModR/M byte indexes into the final table.
 300 //
 301 // If a ModR/M byte is not required, "required" is left unset, and the values
 302 // for each instructionID are identical.
 303 typedef uint16_t InstrUID;
 304
 305 // ModRMDecisionType - describes the type of ModR/M decision, allowing the
 306 // consumer to determine the number of entries in it.
 307 //
 308 // MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
 309 //                  instruction is the same.
 310 // MODRM_SPLITRM  - If the ModR/M byte is between 0x00 and 0xbf, the opcode
 311 //                  corresponds to one instruction; otherwise, it corresponds to
 312 //                  a different instruction.
 313 // MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
 314 //                  divided by 8 is used to select instruction; otherwise, each
 315 //                  value of the ModR/M byte could correspond to a different
 316 //                  instruction.
 317 // MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
 318 //                  corresponds to instructions that use reg field as opcode
 319 // MODRM_FULL     - Potentially, each value of the ModR/M byte could correspond
 320 //                  to a different instruction.
 321 #define MODRMTYPES            \
 322   ENUM_ENTRY(MODRM_ONEENTRY)  \
 323   ENUM_ENTRY(MODRM_SPLITRM)   \
 324   ENUM_ENTRY(MODRM_SPLITMISC)  \
 325   ENUM_ENTRY(MODRM_SPLITREG)  \
 326   ENUM_ENTRY(MODRM_FULL)
 327
 328 #define ENUM_ENTRY(n) n,
 329 enum ModRMDecisionType {
 330   MODRMTYPES
 331   MODRM_max
 332 };
 333 #undef ENUM_ENTRY
 334
 335 #define CASE_ENCODING_RM     \
 336     case ENCODING_RM:        \
 337     case ENCODING_RM_CD2:    \
 338     case ENCODING_RM_CD4:    \
 339     case ENCODING_RM_CD8:    \
 340     case ENCODING_RM_CD16:   \
 341     case ENCODING_RM_CD32:   \
 342     case ENCODING_RM_CD64
 343
 344 #define CASE_ENCODING_VSIB   \
 345     case ENCODING_VSIB:      \
 346     case ENCODING_VSIB_CD2:  \
 347     case ENCODING_VSIB_CD4:  \
 348     case ENCODING_VSIB_CD8:  \
 349     case ENCODING_VSIB_CD16: \
 350     case ENCODING_VSIB_CD32: \
 351     case ENCODING_VSIB_CD64
 352
 353 // Physical encodings of instruction operands.
 354 #define ENCODINGS                                                              \
 355   ENUM_ENTRY(ENCODING_NONE,   "")                                              \
 356   ENUM_ENTRY(ENCODING_REG,    "Register operand in ModR/M byte.")              \
 357   ENUM_ENTRY(ENCODING_RM,     "R/M operand in ModR/M byte.")                   \
 358   ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2")           \
 359   ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4")           \
 360   ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8")           \
 361   ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16")          \
 362   ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32")          \
 363   ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64")          \
 364   ENUM_ENTRY(ENCODING_VSIB,     "VSIB operand in ModR/M byte.")                \
 365   ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2")        \
 366   ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4")        \
 367   ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8")        \
 368   ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16")       \
 369   ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32")       \
 370   ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64")       \
 371   ENUM_ENTRY(ENCODING_VVVV,   "Register operand in VEX.vvvv byte.")            \
 372   ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.")         \
 373   ENUM_ENTRY(ENCODING_IB,     "1-byte immediate")                              \
 374   ENUM_ENTRY(ENCODING_IW,     "2-byte")                                        \
 375   ENUM_ENTRY(ENCODING_ID,     "4-byte")                                        \
 376   ENUM_ENTRY(ENCODING_IO,     "8-byte")                                        \
 377   ENUM_ENTRY(ENCODING_RB,     "(AL..DIL, R8L..R15L) Register code added to "   \
 378                               "the opcode byte")                               \
 379   ENUM_ENTRY(ENCODING_RW,     "(AX..DI, R8W..R15W)")                           \
 380   ENUM_ENTRY(ENCODING_RD,     "(EAX..EDI, R8D..R15D)")                         \
 381   ENUM_ENTRY(ENCODING_RO,     "(RAX..RDI, R8..R15)")                           \
 382   ENUM_ENTRY(ENCODING_FP,     "Position on floating-point stack in ModR/M "    \
 383                               "byte.")                                         \
 384                                                                                \
 385   ENUM_ENTRY(ENCODING_Iv,     "Immediate of operand size")                     \
 386   ENUM_ENTRY(ENCODING_Ia,     "Immediate of address size")                     \
 387   ENUM_ENTRY(ENCODING_IRC,    "Immediate for static rounding control")         \
 388   ENUM_ENTRY(ENCODING_Rv,     "Register code of operand size added to the "    \
 389                               "opcode byte")                                   \
 390   ENUM_ENTRY(ENCODING_CC,     "Condition code encoded in opcode")              \
 391   ENUM_ENTRY(ENCODING_DUP,    "Duplicate of another operand; ID is encoded "   \
 392                               "in type")                                       \
 393   ENUM_ENTRY(ENCODING_SI,     "Source index; encoded in OpSize/Adsize prefix") \
 394   ENUM_ENTRY(ENCODING_DI,     "Destination index; encoded in prefixes")
 395
 396 #define ENUM_ENTRY(n, d) n,
 397 enum OperandEncoding {
 398   ENCODINGS
 399   ENCODING_max
 400 };
 401 #undef ENUM_ENTRY
 402
 403 // Semantic interpretations of instruction operands.
 404 #define TYPES                                                                  \
 405   ENUM_ENTRY(TYPE_NONE,       "")                                              \
 406   ENUM_ENTRY(TYPE_REL,        "immediate address")                             \
 407   ENUM_ENTRY(TYPE_R8,         "1-byte register operand")                       \
 408   ENUM_ENTRY(TYPE_R16,        "2-byte")                                        \
 409   ENUM_ENTRY(TYPE_R32,        "4-byte")                                        \
 410   ENUM_ENTRY(TYPE_R64,        "8-byte")                                        \
 411   ENUM_ENTRY(TYPE_IMM,        "immediate operand")                             \
 412   ENUM_ENTRY(TYPE_UIMM8,      "1-byte unsigned immediate operand")             \
 413   ENUM_ENTRY(TYPE_M,          "Memory operand")                                \
 414   ENUM_ENTRY(TYPE_MVSIBX,     "Memory operand using XMM index")                \
 415   ENUM_ENTRY(TYPE_MVSIBY,     "Memory operand using YMM index")                \
 416   ENUM_ENTRY(TYPE_MVSIBZ,     "Memory operand using ZMM index")                \
 417   ENUM_ENTRY(TYPE_SRCIDX,     "memory at source index")                        \
 418   ENUM_ENTRY(TYPE_DSTIDX,     "memory at destination index")                   \
 419   ENUM_ENTRY(TYPE_MOFFS,      "memory offset (relative to segment base)")      \
 420   ENUM_ENTRY(TYPE_ST,         "Position on the floating-point stack")          \
 421   ENUM_ENTRY(TYPE_MM64,       "8-byte MMX register")                           \
 422   ENUM_ENTRY(TYPE_XMM,        "16-byte")                                       \
 423   ENUM_ENTRY(TYPE_YMM,        "32-byte")                                       \
 424   ENUM_ENTRY(TYPE_ZMM,        "64-byte")                                       \
 425   ENUM_ENTRY(TYPE_VK,         "mask register")                                 \
 426   ENUM_ENTRY(TYPE_VK_PAIR,    "mask register pair")                            \
 427   ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand")                      \
 428   ENUM_ENTRY(TYPE_DEBUGREG,   "Debug register operand")                        \
 429   ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand")                      \
 430   ENUM_ENTRY(TYPE_BNDR,       "MPX bounds register")                           \
 431                                                                                \
 432   ENUM_ENTRY(TYPE_Rv,         "Register operand of operand size")              \
 433   ENUM_ENTRY(TYPE_RELv,       "Immediate address of operand size")             \
 434   ENUM_ENTRY(TYPE_DUP0,       "Duplicate of operand 0")                        \
 435   ENUM_ENTRY(TYPE_DUP1,       "operand 1")                                     \
 436   ENUM_ENTRY(TYPE_DUP2,       "operand 2")                                     \
 437   ENUM_ENTRY(TYPE_DUP3,       "operand 3")                                     \
 438   ENUM_ENTRY(TYPE_DUP4,       "operand 4")                                     \
 439
 440 #define ENUM_ENTRY(n, d) n,
 441 enum OperandType {
 442   TYPES
 443   TYPE_max
 444 };
 445 #undef ENUM_ENTRY
 446
 447 /// The specification for how to extract and interpret one operand.
 448 struct OperandSpecifier {
 449   uint8_t encoding;
 450   uint8_t type;
 451 };
 452
 453 static const unsigned X86_MAX_OPERANDS = 6;
 454
 455 /// Decoding mode for the Intel disassembler.  16-bit, 32-bit, and 64-bit mode
 456 /// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
 457 /// respectively.
 458 enum DisassemblerMode {
 459   MODE_16BIT,
 460   MODE_32BIT,
 461   MODE_64BIT
 462 };
 463
 464 } // namespace X86Disassembler
 465 } // namespace llvm
 466
 467 #endif