lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp

   1 //===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata  -===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 ///
  11 /// This class has methods called by AMDGPUAsmPrinter to accumulate and print
  12 /// the PAL metadata.
  13 //
  14 //===----------------------------------------------------------------------===//
  15 //
  16
  17 #include "AMDGPUPALMetadata.h"
  18 #include "AMDGPU.h"
  19 #include "AMDGPUAsmPrinter.h"
  20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
  21 #include "SIDefines.h"
  22 #include "llvm/BinaryFormat/ELF.h"
  23 #include "llvm/IR/CallingConv.h"
  24 #include "llvm/IR/Constants.h"
  25 #include "llvm/IR/Module.h"
  26 #include "llvm/Support/AMDGPUMetadata.h"
  27 #include "llvm/Support/EndianStream.h"
  28
  29 using namespace llvm;
  30 using namespace llvm::AMDGPU;
  31
  32 // Read the PAL metadata from IR metadata, where it was put by the frontend.
  33 void AMDGPUPALMetadata::readFromIR(Module &M) {
  34   auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack");
  35   if (NamedMD && NamedMD->getNumOperands()) {
  36     // This is the new msgpack format for metadata. It is a NamedMD containing
  37     // an MDTuple containing an MDString containing the msgpack data.
  38     BlobType = ELF::NT_AMDGPU_METADATA;
  39     auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
  40     if (MDN && MDN->getNumOperands()) {
  41       if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
  42         setFromMsgPackBlob(MDS->getString());
  43     }
  44     return;
  45   }
  46   BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;
  47   NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
  48   if (!NamedMD || !NamedMD->getNumOperands())
  49     return;
  50   // This is the old reg=value pair format for metadata. It is a NamedMD
  51   // containing an MDTuple containing a number of MDNodes each of which is an
  52   // integer value, and each two integer values forms a key=value pair that we
  53   // store as Registers[key]=value in the map.
  54   auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
  55   if (!Tuple)
  56     return;
  57   for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
  58     auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
  59     auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
  60     if (!Key || !Val)
  61       continue;
  62     setRegister(Key->getZExtValue(), Val->getZExtValue());
  63   }
  64 }
  65
  66 // Set PAL metadata from a binary blob from the applicable .note record.
  67 // Returns false if bad format.  Blob must remain valid for the lifetime of the
  68 // Metadata.
  69 bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) {
  70   BlobType = Type;
  71   if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA)
  72     return setFromLegacyBlob(Blob);
  73   return setFromMsgPackBlob(Blob);
  74 }
  75
  76 // Set PAL metadata from legacy (array of key=value pairs) blob.
  77 bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
  78   auto Data = reinterpret_cast<const uint32_t *>(Blob.data());
  79   for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
  80     setRegister(Data[I * 2], Data[I * 2 + 1]);
  81   return true;
  82 }
  83
  84 // Set PAL metadata from msgpack blob.
  85 bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
  86   msgpack::Reader Reader(Blob);
  87   return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
  88 }
  89
  90 // Given the calling convention, calculate the register number for rsrc1. In
  91 // principle the register number could change in future hardware, but we know
  92 // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
  93 // we can use fixed values.
  94 static unsigned getRsrc1Reg(CallingConv::ID CC) {
  95   switch (CC) {
  96   default:
  97     return PALMD::R_2E12_COMPUTE_PGM_RSRC1;
  98   case CallingConv::AMDGPU_LS:
  99     return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS;
 100   case CallingConv::AMDGPU_HS:
 101     return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS;
 102   case CallingConv::AMDGPU_ES:
 103     return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES;
 104   case CallingConv::AMDGPU_GS:
 105     return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS;
 106   case CallingConv::AMDGPU_VS:
 107     return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS;
 108   case CallingConv::AMDGPU_PS:
 109     return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS;
 110   }
 111 }
 112
 113 // Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
 114 // with a constant offset to access any non-register shader-specific PAL
 115 // metadata key.
 116 static unsigned getScratchSizeKey(CallingConv::ID CC) {
 117   switch (CC) {
 118   case CallingConv::AMDGPU_PS:
 119     return PALMD::Key::PS_SCRATCH_SIZE;
 120   case CallingConv::AMDGPU_VS:
 121     return PALMD::Key::VS_SCRATCH_SIZE;
 122   case CallingConv::AMDGPU_GS:
 123     return PALMD::Key::GS_SCRATCH_SIZE;
 124   case CallingConv::AMDGPU_ES:
 125     return PALMD::Key::ES_SCRATCH_SIZE;
 126   case CallingConv::AMDGPU_HS:
 127     return PALMD::Key::HS_SCRATCH_SIZE;
 128   case CallingConv::AMDGPU_LS:
 129     return PALMD::Key::LS_SCRATCH_SIZE;
 130   default:
 131     return PALMD::Key::CS_SCRATCH_SIZE;
 132   }
 133 }
 134
 135 // Set the rsrc1 register in the metadata for a particular shader stage.
 136 // In fact this ORs the value into any previous setting of the register.
 137 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) {
 138   setRegister(getRsrc1Reg(CC), Val);
 139 }
 140
 141 // Set the rsrc2 register in the metadata for a particular shader stage.
 142 // In fact this ORs the value into any previous setting of the register.
 143 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) {
 144   setRegister(getRsrc1Reg(CC) + 1, Val);
 145 }
 146
 147 // Set the SPI_PS_INPUT_ENA register in the metadata.
 148 // In fact this ORs the value into any previous setting of the register.
 149 void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) {
 150   setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val);
 151 }
 152
 153 // Set the SPI_PS_INPUT_ADDR register in the metadata.
 154 // In fact this ORs the value into any previous setting of the register.
 155 void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) {
 156   setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val);
 157 }
 158
 159 // Get a register from the metadata, or 0 if not currently set.
 160 unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
 161   auto Regs = getRegisters();
 162   auto It = Regs.find(MsgPackDoc.getNode(Reg));
 163   if (It == Regs.end())
 164     return 0;
 165   auto N = It->second;
 166   if (N.getKind() != msgpack::Type::UInt)
 167     return 0;
 168   return N.getUInt();
 169 }
 170
 171 // Set a register in the metadata.
 172 // In fact this ORs the value into any previous setting of the register.
 173 void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
 174   if (!isLegacy()) {
 175     // In the new MsgPack format, ignore register numbered >= 0x10000000. It
 176     // is a PAL ABI pseudo-register in the old non-MsgPack format.
 177     if (Reg >= 0x10000000)
 178       return;
 179   }
 180   auto &N = getRegisters()[MsgPackDoc.getNode(Reg)];
 181   if (N.getKind() == msgpack::Type::UInt)
 182     Val |= N.getUInt();
 183   N = N.getDocument()->getNode(Val);
 184 }
 185
 186 // Set the entry point name for one shader.
 187 void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
 188   if (isLegacy())
 189     return;
 190   // Msgpack format.
 191   getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true);
 192 }
 193
 194 // Set the number of used vgprs in the metadata. This is an optional
 195 // advisory record for logging etc; wave dispatch actually uses the rsrc1
 196 // register for the shader stage to determine the number of vgprs to
 197 // allocate.
 198 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) {
 199   if (isLegacy()) {
 200     // Old non-msgpack format.
 201     unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
 202                                PALMD::Key::VS_NUM_USED_VGPRS -
 203                                PALMD::Key::VS_SCRATCH_SIZE;
 204     setRegister(NumUsedVgprsKey, Val);
 205     return;
 206   }
 207   // Msgpack format.
 208   getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val);
 209 }
 210
 211 // Set the number of used sgprs in the metadata. This is an optional advisory
 212 // record for logging etc; wave dispatch actually uses the rsrc1 register for
 213 // the shader stage to determine the number of sgprs to allocate.
 214 void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) {
 215   if (isLegacy()) {
 216     // Old non-msgpack format.
 217     unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
 218                                PALMD::Key::VS_NUM_USED_SGPRS -
 219                                PALMD::Key::VS_SCRATCH_SIZE;
 220     setRegister(NumUsedSgprsKey, Val);
 221     return;
 222   }
 223   // Msgpack format.
 224   getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val);
 225 }
 226
 227 // Set the scratch size in the metadata.
 228 void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) {
 229   if (isLegacy()) {
 230     // Old non-msgpack format.
 231     setRegister(getScratchSizeKey(CC), Val);
 232     return;
 233   }
 234   // Msgpack format.
 235   getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val);
 236 }
 237
 238 // Set the hardware register bit in PAL metadata to enable wave32 on the
 239 // shader of the given calling convention.
 240 void AMDGPUPALMetadata::setWave32(unsigned CC) {
 241   switch (CC) {
 242   case CallingConv::AMDGPU_HS:
 243     setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1));
 244     break;
 245   case CallingConv::AMDGPU_GS:
 246     setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1));
 247     break;
 248   case CallingConv::AMDGPU_VS:
 249     setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1));
 250     break;
 251   case CallingConv::AMDGPU_PS:
 252     setRegister(PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1));
 253     break;
 254   case CallingConv::AMDGPU_CS:
 255     setRegister(PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR,
 256                 S_00B800_CS_W32_EN(1));
 257     break;
 258   }
 259 }
 260
 261 // Convert a register number to name, for display by toString().
 262 // Returns nullptr if none.
 263 static const char *getRegisterName(unsigned RegNum) {
 264   // Table of registers.
 265   static const struct RegInfo {
 266     unsigned Num;
 267     const char *Name;
 268   } RegInfoTable[] = {
 269       // Registers that code generation sets/modifies metadata for.
 270       {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"},
 271       {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"},
 272       {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"},
 273       {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"},
 274       {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"},
 275       {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"},
 276       {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"},
 277       {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"},
 278       {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"},
 279       {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"},
 280       {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"},
 281       {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"},
 282       {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"},
 283       {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"},
 284       {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"},
 285       {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"},
 286       {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"},
 287       {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"},
 288       {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"},
 289
 290       // Registers not known to code generation.
 291       {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
 292       {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"},
 293       {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"},
 294       {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"},
 295       {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"},
 296       {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"},
 297
 298       {0xa1c3, "SPI_SHADER_POS_FORMAT"},
 299       {0xa1b1, "SPI_VS_OUT_CONFIG"},
 300       {0xa207, "PA_CL_VS_OUT_CNTL"},
 301       {0xa204, "PA_CL_CLIP_CNTL"},
 302       {0xa206, "PA_CL_VTE_CNTL"},
 303       {0xa2f9, "PA_SU_VTX_CNTL"},
 304       {0xa293, "PA_SC_MODE_CNTL_1"},
 305       {0xa2a1, "VGT_PRIMITIVEID_EN"},
 306       {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"},
 307       {0x2e18, "COMPUTE_TMPRING_SIZE"},
 308       {0xa1b5, "SPI_INTERP_CONTROL_0"},
 309       {0xa1ba, "SPI_TMPRING_SIZE"},
 310       {0xa1c4, "SPI_SHADER_Z_FORMAT"},
 311       {0xa1c5, "SPI_SHADER_COL_FORMAT"},
 312       {0xa203, "DB_SHADER_CONTROL"},
 313       {0xa08f, "CB_SHADER_MASK"},
 314       {0xa191, "SPI_PS_INPUT_CNTL_0"},
 315       {0xa192, "SPI_PS_INPUT_CNTL_1"},
 316       {0xa193, "SPI_PS_INPUT_CNTL_2"},
 317       {0xa194, "SPI_PS_INPUT_CNTL_3"},
 318       {0xa195, "SPI_PS_INPUT_CNTL_4"},
 319       {0xa196, "SPI_PS_INPUT_CNTL_5"},
 320       {0xa197, "SPI_PS_INPUT_CNTL_6"},
 321       {0xa198, "SPI_PS_INPUT_CNTL_7"},
 322       {0xa199, "SPI_PS_INPUT_CNTL_8"},
 323       {0xa19a, "SPI_PS_INPUT_CNTL_9"},
 324       {0xa19b, "SPI_PS_INPUT_CNTL_10"},
 325       {0xa19c, "SPI_PS_INPUT_CNTL_11"},
 326       {0xa19d, "SPI_PS_INPUT_CNTL_12"},
 327       {0xa19e, "SPI_PS_INPUT_CNTL_13"},
 328       {0xa19f, "SPI_PS_INPUT_CNTL_14"},
 329       {0xa1a0, "SPI_PS_INPUT_CNTL_15"},
 330       {0xa1a1, "SPI_PS_INPUT_CNTL_16"},
 331       {0xa1a2, "SPI_PS_INPUT_CNTL_17"},
 332       {0xa1a3, "SPI_PS_INPUT_CNTL_18"},
 333       {0xa1a4, "SPI_PS_INPUT_CNTL_19"},
 334       {0xa1a5, "SPI_PS_INPUT_CNTL_20"},
 335       {0xa1a6, "SPI_PS_INPUT_CNTL_21"},
 336       {0xa1a7, "SPI_PS_INPUT_CNTL_22"},
 337       {0xa1a8, "SPI_PS_INPUT_CNTL_23"},
 338       {0xa1a9, "SPI_PS_INPUT_CNTL_24"},
 339       {0xa1aa, "SPI_PS_INPUT_CNTL_25"},
 340       {0xa1ab, "SPI_PS_INPUT_CNTL_26"},
 341       {0xa1ac, "SPI_PS_INPUT_CNTL_27"},
 342       {0xa1ad, "SPI_PS_INPUT_CNTL_28"},
 343       {0xa1ae, "SPI_PS_INPUT_CNTL_29"},
 344       {0xa1af, "SPI_PS_INPUT_CNTL_30"},
 345       {0xa1b0, "SPI_PS_INPUT_CNTL_31"},
 346
 347       {0xa2ce, "VGT_GS_MAX_VERT_OUT"},
 348       {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"},
 349       {0xa290, "VGT_GS_MODE"},
 350       {0xa291, "VGT_GS_ONCHIP_CNTL"},
 351       {0xa2d7, "VGT_GS_VERT_ITEMSIZE"},
 352       {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"},
 353       {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"},
 354       {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"},
 355       {0xa298, "VGT_GSVS_RING_OFFSET_1"},
 356       {0xa299, "VGT_GSVS_RING_OFFSET_2"},
 357       {0xa29a, "VGT_GSVS_RING_OFFSET_3"},
 358
 359       {0xa2e4, "VGT_GS_INSTANCE_CNT"},
 360       {0xa297, "VGT_GS_PER_VS"},
 361       {0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
 362       {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
 363
 364       {0xa2ad, "VGT_REUSE_OFF"},
 365       {0xa1b8, "SPI_BARYC_CNTL"},
 366
 367       {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"},
 368       {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"},
 369       {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"},
 370       {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"},
 371       {0x2c50, "SPI_SHADER_USER_DATA_VS_4"},
 372       {0x2c51, "SPI_SHADER_USER_DATA_VS_5"},
 373       {0x2c52, "SPI_SHADER_USER_DATA_VS_6"},
 374       {0x2c53, "SPI_SHADER_USER_DATA_VS_7"},
 375       {0x2c54, "SPI_SHADER_USER_DATA_VS_8"},
 376       {0x2c55, "SPI_SHADER_USER_DATA_VS_9"},
 377       {0x2c56, "SPI_SHADER_USER_DATA_VS_10"},
 378       {0x2c57, "SPI_SHADER_USER_DATA_VS_11"},
 379       {0x2c58, "SPI_SHADER_USER_DATA_VS_12"},
 380       {0x2c59, "SPI_SHADER_USER_DATA_VS_13"},
 381       {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"},
 382       {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"},
 383       {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"},
 384       {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"},
 385       {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"},
 386       {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"},
 387       {0x2c60, "SPI_SHADER_USER_DATA_VS_20"},
 388       {0x2c61, "SPI_SHADER_USER_DATA_VS_21"},
 389       {0x2c62, "SPI_SHADER_USER_DATA_VS_22"},
 390       {0x2c63, "SPI_SHADER_USER_DATA_VS_23"},
 391       {0x2c64, "SPI_SHADER_USER_DATA_VS_24"},
 392       {0x2c65, "SPI_SHADER_USER_DATA_VS_25"},
 393       {0x2c66, "SPI_SHADER_USER_DATA_VS_26"},
 394       {0x2c67, "SPI_SHADER_USER_DATA_VS_27"},
 395       {0x2c68, "SPI_SHADER_USER_DATA_VS_28"},
 396       {0x2c69, "SPI_SHADER_USER_DATA_VS_29"},
 397       {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"},
 398       {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"},
 399
 400       {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"},
 401       {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"},
 402       {0x2cce, "SPI_SHADER_USER_DATA_ES_2"},
 403       {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"},
 404       {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"},
 405       {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"},
 406       {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"},
 407       {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"},
 408       {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"},
 409       {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"},
 410       {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"},
 411       {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"},
 412       {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"},
 413       {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"},
 414       {0x2cda, "SPI_SHADER_USER_DATA_ES_14"},
 415       {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"},
 416       {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"},
 417       {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"},
 418       {0x2cde, "SPI_SHADER_USER_DATA_ES_18"},
 419       {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"},
 420       {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"},
 421       {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"},
 422       {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"},
 423       {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"},
 424       {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"},
 425       {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"},
 426       {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"},
 427       {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"},
 428       {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"},
 429       {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"},
 430       {0x2cea, "SPI_SHADER_USER_DATA_ES_30"},
 431       {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"},
 432
 433       {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"},
 434       {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"},
 435       {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"},
 436       {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"},
 437       {0x2c10, "SPI_SHADER_USER_DATA_PS_4"},
 438       {0x2c11, "SPI_SHADER_USER_DATA_PS_5"},
 439       {0x2c12, "SPI_SHADER_USER_DATA_PS_6"},
 440       {0x2c13, "SPI_SHADER_USER_DATA_PS_7"},
 441       {0x2c14, "SPI_SHADER_USER_DATA_PS_8"},
 442       {0x2c15, "SPI_SHADER_USER_DATA_PS_9"},
 443       {0x2c16, "SPI_SHADER_USER_DATA_PS_10"},
 444       {0x2c17, "SPI_SHADER_USER_DATA_PS_11"},
 445       {0x2c18, "SPI_SHADER_USER_DATA_PS_12"},
 446       {0x2c19, "SPI_SHADER_USER_DATA_PS_13"},
 447       {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"},
 448       {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"},
 449       {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"},
 450       {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"},
 451       {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"},
 452       {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"},
 453       {0x2c20, "SPI_SHADER_USER_DATA_PS_20"},
 454       {0x2c21, "SPI_SHADER_USER_DATA_PS_21"},
 455       {0x2c22, "SPI_SHADER_USER_DATA_PS_22"},
 456       {0x2c23, "SPI_SHADER_USER_DATA_PS_23"},
 457       {0x2c24, "SPI_SHADER_USER_DATA_PS_24"},
 458       {0x2c25, "SPI_SHADER_USER_DATA_PS_25"},
 459       {0x2c26, "SPI_SHADER_USER_DATA_PS_26"},
 460       {0x2c27, "SPI_SHADER_USER_DATA_PS_27"},
 461       {0x2c28, "SPI_SHADER_USER_DATA_PS_28"},
 462       {0x2c29, "SPI_SHADER_USER_DATA_PS_29"},
 463       {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"},
 464       {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"},
 465
 466       {0x2e40, "COMPUTE_USER_DATA_0"},
 467       {0x2e41, "COMPUTE_USER_DATA_1"},
 468       {0x2e42, "COMPUTE_USER_DATA_2"},
 469       {0x2e43, "COMPUTE_USER_DATA_3"},
 470       {0x2e44, "COMPUTE_USER_DATA_4"},
 471       {0x2e45, "COMPUTE_USER_DATA_5"},
 472       {0x2e46, "COMPUTE_USER_DATA_6"},
 473       {0x2e47, "COMPUTE_USER_DATA_7"},
 474       {0x2e48, "COMPUTE_USER_DATA_8"},
 475       {0x2e49, "COMPUTE_USER_DATA_9"},
 476       {0x2e4a, "COMPUTE_USER_DATA_10"},
 477       {0x2e4b, "COMPUTE_USER_DATA_11"},
 478       {0x2e4c, "COMPUTE_USER_DATA_12"},
 479       {0x2e4d, "COMPUTE_USER_DATA_13"},
 480       {0x2e4e, "COMPUTE_USER_DATA_14"},
 481       {0x2e4f, "COMPUTE_USER_DATA_15"},
 482
 483       {0x2e07, "COMPUTE_NUM_THREAD_X"},
 484       {0x2e08, "COMPUTE_NUM_THREAD_Y"},
 485       {0x2e09, "COMPUTE_NUM_THREAD_Z"},
 486       {0xa2db, "VGT_TF_PARAM"},
 487       {0xa2d6, "VGT_LS_HS_CONFIG"},
 488       {0xa287, "VGT_HOS_MIN_TESS_LEVEL"},
 489       {0xa286, "VGT_HOS_MAX_TESS_LEVEL"},
 490       {0xa2f8, "PA_SC_AA_CONFIG"},
 491       {0xa310, "PA_SC_SHADER_CONTROL"},
 492       {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
 493
 494       {0x2d0c, "SPI_SHADER_USER_DATA_LS_0"},
 495       {0x2d0d, "SPI_SHADER_USER_DATA_LS_1"},
 496       {0x2d0e, "SPI_SHADER_USER_DATA_LS_2"},
 497       {0x2d0f, "SPI_SHADER_USER_DATA_LS_3"},
 498       {0x2d10, "SPI_SHADER_USER_DATA_LS_4"},
 499       {0x2d11, "SPI_SHADER_USER_DATA_LS_5"},
 500       {0x2d12, "SPI_SHADER_USER_DATA_LS_6"},
 501       {0x2d13, "SPI_SHADER_USER_DATA_LS_7"},
 502       {0x2d14, "SPI_SHADER_USER_DATA_LS_8"},
 503       {0x2d15, "SPI_SHADER_USER_DATA_LS_9"},
 504       {0x2d16, "SPI_SHADER_USER_DATA_LS_10"},
 505       {0x2d17, "SPI_SHADER_USER_DATA_LS_11"},
 506       {0x2d18, "SPI_SHADER_USER_DATA_LS_12"},
 507       {0x2d19, "SPI_SHADER_USER_DATA_LS_13"},
 508       {0x2d1a, "SPI_SHADER_USER_DATA_LS_14"},
 509       {0x2d1b, "SPI_SHADER_USER_DATA_LS_15"},
 510       {0x2d1c, "SPI_SHADER_USER_DATA_LS_16"},
 511       {0x2d1d, "SPI_SHADER_USER_DATA_LS_17"},
 512       {0x2d1e, "SPI_SHADER_USER_DATA_LS_18"},
 513       {0x2d1f, "SPI_SHADER_USER_DATA_LS_19"},
 514       {0x2d20, "SPI_SHADER_USER_DATA_LS_20"},
 515       {0x2d21, "SPI_SHADER_USER_DATA_LS_21"},
 516       {0x2d22, "SPI_SHADER_USER_DATA_LS_22"},
 517       {0x2d23, "SPI_SHADER_USER_DATA_LS_23"},
 518       {0x2d24, "SPI_SHADER_USER_DATA_LS_24"},
 519       {0x2d25, "SPI_SHADER_USER_DATA_LS_25"},
 520       {0x2d26, "SPI_SHADER_USER_DATA_LS_26"},
 521       {0x2d27, "SPI_SHADER_USER_DATA_LS_27"},
 522       {0x2d28, "SPI_SHADER_USER_DATA_LS_28"},
 523       {0x2d29, "SPI_SHADER_USER_DATA_LS_29"},
 524       {0x2d2a, "SPI_SHADER_USER_DATA_LS_30"},
 525       {0x2d2b, "SPI_SHADER_USER_DATA_LS_31"},
 526
 527       {0xa2aa, "IA_MULTI_VGT_PARAM"},
 528       {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
 529       {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
 530       {0xa2e5, "VGT_STRMOUT_CONFIG"},
 531       {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
 532       {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
 533       {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
 534       {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
 535       {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
 536
 537       {0, nullptr}};
 538   auto Entry = RegInfoTable;
 539   for (; Entry->Num && Entry->Num != RegNum; ++Entry)
 540     ;
 541   return Entry->Name;
 542 }
 543
 544 // Convert the accumulated PAL metadata into an asm directive.
 545 void AMDGPUPALMetadata::toString(std::string &String) {
 546   String.clear();
 547   if (!BlobType)
 548     return;
 549   raw_string_ostream Stream(String);
 550   if (isLegacy()) {
 551     if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
 552       return;
 553     // Old linear reg=val format.
 554     Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
 555     auto Regs = getRegisters();
 556     for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
 557       if (I != Regs.begin())
 558         Stream << ',';
 559       unsigned Reg = I->first.getUInt();
 560       unsigned Val = I->second.getUInt();
 561       Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val);
 562     }
 563     Stream << '\n';
 564     return;
 565   }
 566
 567   // New msgpack-based format -- output as YAML (with unsigned numbers in hex),
 568   // but first change the registers map to use names.
 569   MsgPackDoc.setHexMode();
 570   auto &RegsObj = refRegisters();
 571   auto OrigRegs = RegsObj.getMap();
 572   RegsObj = MsgPackDoc.getMapNode();
 573   for (auto I : OrigRegs) {
 574     auto Key = I.first;
 575     if (const char *RegName = getRegisterName(Key.getUInt())) {
 576       std::string KeyName = Key.toString();
 577       KeyName += " (";
 578       KeyName += RegName;
 579       KeyName += ')';
 580       Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true);
 581     }
 582     RegsObj.getMap()[Key] = I.second;
 583   }
 584
 585   // Output as YAML.
 586   Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
 587   MsgPackDoc.toYAML(Stream);
 588   Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
 589
 590   // Restore original registers map.
 591   RegsObj = OrigRegs;
 592 }
 593
 594 // Convert the accumulated PAL metadata into a binary blob for writing as
 595 // a .note record of the specified AMD type. Returns an empty blob if
 596 // there is no PAL metadata,
 597 void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
 598   if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA)
 599     toLegacyBlob(Blob);
 600   else if (Type)
 601     toMsgPackBlob(Blob);
 602 }
 603
 604 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
 605   Blob.clear();
 606   auto Registers = getRegisters();
 607   if (Registers.getMap().empty())
 608     return;
 609   raw_string_ostream OS(Blob);
 610   support::endian::Writer EW(OS, support::endianness::little);
 611   for (auto I : Registers.getMap()) {
 612     EW.write(uint32_t(I.first.getUInt()));
 613     EW.write(uint32_t(I.second.getUInt()));
 614   }
 615 }
 616
 617 void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
 618   Blob.clear();
 619   MsgPackDoc.writeToBlob(Blob);
 620 }
 621
 622 // Set PAL metadata from YAML text. Returns false if failed.
 623 bool AMDGPUPALMetadata::setFromString(StringRef S) {
 624   BlobType = ELF::NT_AMDGPU_METADATA;
 625   if (!MsgPackDoc.fromYAML(S))
 626     return false;
 627
 628   // In the registers map, some keys may be of the form "0xa191
 629   // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
 630   // string. We need to turn it into a number.
 631   auto &RegsObj = refRegisters();
 632   auto OrigRegs = RegsObj;
 633   RegsObj = MsgPackDoc.getMapNode();
 634   Registers = RegsObj.getMap();
 635   bool Ok = true;
 636   for (auto I : OrigRegs.getMap()) {
 637     auto Key = I.first;
 638     if (Key.getKind() == msgpack::Type::String) {
 639       StringRef S = Key.getString();
 640       uint64_t Val;
 641       if (S.consumeInteger(0, Val)) {
 642         Ok = false;
 643         errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
 644         continue;
 645       }
 646       Key = MsgPackDoc.getNode(uint64_t(Val));
 647     }
 648     Registers.getMap()[Key] = I.second;
 649   }
 650   return Ok;
 651 }
 652
 653 // Reference (create if necessary) the node for the registers map.
 654 msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
 655   auto &N =
 656       MsgPackDoc.getRoot()
 657           .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
 658           .getArray(/*Convert=*/true)[0]
 659           .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")];
 660   N.getMap(/*Convert=*/true);
 661   return N;
 662 }
 663
 664 // Get (create if necessary) the registers map.
 665 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
 666   if (Registers.isEmpty())
 667     Registers = refRegisters();
 668   return Registers.getMap();
 669 }
 670
 671 // Return the PAL metadata hardware shader stage name.
 672 static const char *getStageName(CallingConv::ID CC) {
 673   switch (CC) {
 674   case CallingConv::AMDGPU_PS:
 675     return ".ps";
 676   case CallingConv::AMDGPU_VS:
 677     return ".vs";
 678   case CallingConv::AMDGPU_GS:
 679     return ".gs";
 680   case CallingConv::AMDGPU_ES:
 681     return ".es";
 682   case CallingConv::AMDGPU_HS:
 683     return ".hs";
 684   case CallingConv::AMDGPU_LS:
 685     return ".ls";
 686   default:
 687     return ".cs";
 688   }
 689 }
 690
 691 // Get (create if necessary) the .hardware_stages entry for the given calling
 692 // convention.
 693 msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
 694   if (HwStages.isEmpty())
 695     HwStages = MsgPackDoc.getRoot()
 696                    .getMap(/*Convert=*/true)["amdpal.pipelines"]
 697                    .getArray(/*Convert=*/true)[0]
 698                    .getMap(/*Convert=*/true)[".hardware_stages"]
 699                    .getMap(/*Convert=*/true);
 700   return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
 701 }
 702
 703 // Get .note record vendor name of metadata blob to be emitted.
 704 const char *AMDGPUPALMetadata::getVendor() const {
 705   return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
 706 }
 707
 708 // Get .note record type of metadata blob to be emitted:
 709 // ELF::NT_AMD_AMDGPU_PAL_METADATA (legacy key=val format), or
 710 // ELF::NT_AMDGPU_METADATA (MsgPack format), or
 711 // 0 (no PAL metadata).
 712 unsigned AMDGPUPALMetadata::getType() const {
 713   return BlobType;
 714 }
 715
 716 // Return whether the blob type is legacy PAL metadata.
 717 bool AMDGPUPALMetadata::isLegacy() const {
 718   return BlobType == ELF::NT_AMD_AMDGPU_PAL_METADATA;
 719 }
 720
 721 // Set legacy PAL metadata format.
 722 void AMDGPUPALMetadata::setLegacy() {
 723   BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;
 724 }
 725