1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the Thumb2 instruction set.
11 //===----------------------------------------------------------------------===//
13 // IT block predicate field
14 def it_pred_asmoperand : AsmOperandClass {
15 let Name = "ITCondCode";
16 let ParserMethod = "parseITCondCode";
18 def it_pred : Operand<i32> {
19 let PrintMethod = "printMandatoryPredicateOperand";
20 let ParserMatchClass = it_pred_asmoperand;
23 // IT block condition mask
24 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
25 def it_mask : Operand<i32> {
26 let PrintMethod = "printThumbITMask";
27 let ParserMatchClass = it_mask_asmoperand;
28 let EncoderMethod = "getITMaskOpValue";
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 def mve_shift_imm : AsmOperandClass {
44 let Name = "MVELongShift";
45 let RenderMethod = "addImmOperands";
46 let DiagnosticString = "operand must be an immediate in the range [1,32]";
48 def long_shift : Operand<i32>,
49 ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> {
50 let ParserMatchClass = mve_shift_imm;
51 let DecoderMethod = "DecodeLongShiftOperand";
54 // Shifted operands. No register controlled shifts for Thumb2.
55 // Note: We do not support rrx shifted operands yet.
56 def t2_so_reg : Operand<i32>, // reg imm
57 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
59 let EncoderMethod = "getT2SORegOpValue";
60 let PrintMethod = "printT2SOOperand";
61 let DecoderMethod = "DecodeSORegImmOperand";
62 let ParserMatchClass = ShiftedImmAsmOperand;
63 let MIOperandInfo = (ops rGPR, i32imm);
66 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
67 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
68 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
72 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
73 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
74 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
78 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
79 // described for so_imm_notSext def below, with sign extension from 16
81 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
82 APInt apIntN = N->getAPIntValue();
83 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
84 return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
87 // t2_so_imm - Match a 32-bit immediate operand, which is an
88 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
89 // immediate splatted into multiple bytes of the word.
90 def t2_so_imm_asmoperand : AsmOperandClass {
92 let RenderMethod = "addImmOperands";
95 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
96 return ARM_AM::getT2SOImmVal(Imm) != -1;
98 let ParserMatchClass = t2_so_imm_asmoperand;
99 let EncoderMethod = "getT2SOImmOpValue";
100 let DecoderMethod = "DecodeT2SOImm";
103 // t2_so_imm_not - Match an immediate that is a complement
105 // Note: this pattern doesn't require an encoder method and such, as it's
106 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
107 // is handled by the destination instructions, which use t2_so_imm.
108 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
109 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
110 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
111 }], t2_so_imm_not_XFORM> {
112 let ParserMatchClass = t2_so_imm_not_asmoperand;
115 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
116 // if the upper 16 bits are zero.
117 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
118 APInt apIntN = N->getAPIntValue();
119 if (!apIntN.isIntN(16)) return false;
120 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
121 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
122 }], t2_so_imm_notSext16_XFORM> {
123 let ParserMatchClass = t2_so_imm_not_asmoperand;
126 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
127 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
128 def t2_so_imm_neg : Operand<i32>, ImmLeaf<i32, [{
129 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
130 }], t2_so_imm_neg_XFORM> {
131 let ParserMatchClass = t2_so_imm_neg_asmoperand;
134 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0,4095].
135 def imm0_4095_asmoperand: ImmAsmOperand<0,4095> { let Name = "Imm0_4095"; }
136 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
137 return Imm >= 0 && Imm < 4096;
139 let ParserMatchClass = imm0_4095_asmoperand;
142 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
143 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
144 return (uint32_t)(-N->getZExtValue()) < 4096;
146 let ParserMatchClass = imm0_4095_neg_asmoperand;
149 def imm1_255_neg : PatLeaf<(i32 imm), [{
150 uint32_t Val = -N->getZExtValue();
151 return (Val > 0 && Val < 255);
154 def imm0_255_not : PatLeaf<(i32 imm), [{
155 return (uint32_t)(~N->getZExtValue()) < 255;
158 def lo5AllOne : PatLeaf<(i32 imm), [{
159 // Returns true if all low 5-bits are 1.
160 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
163 // Define Thumb2 specific addressing modes.
165 // t2_addr_offset_none := reg
166 def MemNoOffsetT2AsmOperand
167 : AsmOperandClass { let Name = "MemNoOffsetT2"; }
168 def t2_addr_offset_none : MemOperand {
169 let PrintMethod = "printAddrMode7Operand";
170 let DecoderMethod = "DecodeGPRnopcRegisterClass";
171 let ParserMatchClass = MemNoOffsetT2AsmOperand;
172 let MIOperandInfo = (ops GPRnopc:$base);
175 // t2_nosp_addr_offset_none := reg
176 def MemNoOffsetT2NoSpAsmOperand
177 : AsmOperandClass { let Name = "MemNoOffsetT2NoSp"; }
178 def t2_nosp_addr_offset_none : MemOperand {
179 let PrintMethod = "printAddrMode7Operand";
180 let DecoderMethod = "DecoderGPRRegisterClass";
181 let ParserMatchClass = MemNoOffsetT2NoSpAsmOperand;
182 let MIOperandInfo = (ops rGPR:$base);
185 // t2addrmode_imm12 := reg + imm12
186 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
187 def t2addrmode_imm12 : MemOperand,
188 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
189 let PrintMethod = "printAddrModeImm12Operand<false>";
190 let EncoderMethod = "getAddrModeImm12OpValue";
191 let DecoderMethod = "DecodeT2AddrModeImm12";
192 let ParserMatchClass = t2addrmode_imm12_asmoperand;
193 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
196 // t2ldrlabel := imm12
197 def t2ldrlabel : Operand<i32> {
198 let EncoderMethod = "getAddrModeImm12OpValue";
199 let PrintMethod = "printThumbLdrLabelOperand";
202 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
203 def t2ldr_pcrel_imm12 : Operand<i32> {
204 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
205 // used for assembler pseudo instruction and maps to t2ldrlabel, so
206 // doesn't need encoder or print methods of its own.
209 // ADR instruction labels.
210 def t2adrlabel : Operand<i32> {
211 let EncoderMethod = "getT2AdrLabelOpValue";
212 let PrintMethod = "printAdrLabelOperand<0>";
215 // t2addrmode_posimm8 := reg + imm8
216 def MemPosImm8OffsetAsmOperand : AsmOperandClass {
217 let Name="MemPosImm8Offset";
218 let RenderMethod = "addMemImmOffsetOperands";
220 def t2addrmode_posimm8 : MemOperand {
221 let PrintMethod = "printT2AddrModeImm8Operand<false>";
222 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
223 let DecoderMethod = "DecodeT2AddrModeImm8";
224 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
225 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
228 // t2addrmode_negimm8 := reg - imm8
229 def MemNegImm8OffsetAsmOperand : AsmOperandClass {
230 let Name="MemNegImm8Offset";
231 let RenderMethod = "addMemImmOffsetOperands";
233 def t2addrmode_negimm8 : MemOperand,
234 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
235 let PrintMethod = "printT2AddrModeImm8Operand<false>";
236 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
237 let DecoderMethod = "DecodeT2AddrModeImm8";
238 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
239 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
242 // t2addrmode_imm8 := reg +/- imm8
243 def MemImm8OffsetAsmOperand : AsmOperandClass {
244 let Name = "MemImm8Offset";
245 let RenderMethod = "addMemImmOffsetOperands";
247 class T2AddrMode_Imm8 : MemOperand,
248 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
249 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
250 let DecoderMethod = "DecodeT2AddrModeImm8";
251 let ParserMatchClass = MemImm8OffsetAsmOperand;
252 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
255 def t2addrmode_imm8 : T2AddrMode_Imm8 {
256 let PrintMethod = "printT2AddrModeImm8Operand<false>";
259 def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
260 let PrintMethod = "printT2AddrModeImm8Operand<true>";
263 def t2am_imm8_offset : MemOperand,
264 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
265 [], [SDNPWantRoot]> {
266 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
267 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
268 let DecoderMethod = "DecodeT2Imm8";
271 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
272 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
273 class T2AddrMode_Imm8s4 : MemOperand {
274 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
275 let DecoderMethod = "DecodeT2AddrModeImm8s4";
276 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
277 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
280 def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
281 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
284 def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
285 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
288 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
289 def t2am_imm8s4_offset : MemOperand {
290 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
291 let EncoderMethod = "getT2ScaledImmOpValue<8,2>";
292 let DecoderMethod = "DecodeT2Imm8S4";
295 // t2addrmode_imm7s4 := reg +/- (imm7 << 2)
296 def MemImm7s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm7s4Offset";}
297 class T2AddrMode_Imm7s4 : MemOperand {
298 let EncoderMethod = "getT2AddrModeImm7s4OpValue";
299 let DecoderMethod = "DecodeT2AddrModeImm7<2,0>";
300 let ParserMatchClass = MemImm7s4OffsetAsmOperand;
301 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
304 def t2addrmode_imm7s4 : T2AddrMode_Imm7s4 {
305 // They are printed the same way as the imm8 version
306 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
309 def t2addrmode_imm7s4_pre : T2AddrMode_Imm7s4 {
310 // They are printed the same way as the imm8 version
311 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
314 def t2am_imm7s4_offset_asmoperand : AsmOperandClass { let Name = "Imm7s4"; }
315 def t2am_imm7s4_offset : MemOperand {
316 // They are printed the same way as the imm8 version
317 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
318 let ParserMatchClass = t2am_imm7s4_offset_asmoperand;
319 let EncoderMethod = "getT2ScaledImmOpValue<7,2>";
320 let DecoderMethod = "DecodeT2Imm7S4";
323 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
324 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
325 let Name = "MemImm0_1020s4Offset";
327 def t2addrmode_imm0_1020s4 : MemOperand,
328 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
329 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
330 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
331 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
332 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
333 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
336 // t2addrmode_so_reg := reg + (reg << imm2)
337 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
338 def t2addrmode_so_reg : MemOperand,
339 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
340 let PrintMethod = "printT2AddrModeSoRegOperand";
341 let EncoderMethod = "getT2AddrModeSORegOpValue";
342 let DecoderMethod = "DecodeT2AddrModeSOReg";
343 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
344 let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm);
347 // Addresses for the TBB/TBH instructions.
348 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
349 def addrmode_tbb : MemOperand {
350 let PrintMethod = "printAddrModeTBB";
351 let ParserMatchClass = addrmode_tbb_asmoperand;
352 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
354 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
355 def addrmode_tbh : MemOperand {
356 let PrintMethod = "printAddrModeTBH";
357 let ParserMatchClass = addrmode_tbh_asmoperand;
358 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
361 // Define ARMv8.1-M specific addressing modes.
363 // Label operands for BF/BFL/WLS/DLS/LE
364 class BFLabelOp<string signed, string isNeg, string zeroPermitted, string size,
367 let EncoderMethod = !strconcat("getBFTargetOpValue<", isNeg, ", ",
369 let OperandType = "OPERAND_PCREL";
370 let DecoderMethod = !strconcat("DecodeBFLabelOperand<", signed, ", ",
371 isNeg, ", ", zeroPermitted, ", ", size, ">");
373 def bflabel_u4 : BFLabelOp<"false", "false", "false", "4", "ARM::fixup_bf_branch">;
374 def bflabel_s12 : BFLabelOp<"true", "false", "true", "12", "ARM::fixup_bfc_target">;
375 def bflabel_s16 : BFLabelOp<"true", "false", "true", "16", "ARM::fixup_bf_target">;
376 def bflabel_s18 : BFLabelOp<"true", "false", "true", "18", "ARM::fixup_bfl_target">;
378 def wlslabel_u11_asmoperand : AsmOperandClass {
379 let Name = "WLSLabel";
380 let RenderMethod = "addImmOperands";
381 let PredicateMethod = "isUnsignedOffset<11, 1>";
382 let DiagnosticString =
383 "loop end is out of range or not a positive multiple of 2";
385 def wlslabel_u11 : BFLabelOp<"false", "false", "true", "11", "ARM::fixup_wls"> {
386 let ParserMatchClass = wlslabel_u11_asmoperand;
388 def lelabel_u11_asmoperand : AsmOperandClass {
389 let Name = "LELabel";
390 let RenderMethod = "addImmOperands";
391 let PredicateMethod = "isLEOffset";
392 let DiagnosticString =
393 "loop start is out of range or not a negative multiple of 2";
395 def lelabel_u11 : BFLabelOp<"false", "true", "true", "11", "ARM::fixup_le"> {
396 let ParserMatchClass = lelabel_u11_asmoperand;
399 def bfafter_target : Operand<OtherVT> {
400 let EncoderMethod = "getBFAfterTargetOpValue";
401 let OperandType = "OPERAND_PCREL";
402 let DecoderMethod = "DecodeBFAfterTargetOperand";
405 // pred operand excluding AL
406 def pred_noal_asmoperand : AsmOperandClass {
407 let Name = "CondCodeNoAL";
408 let RenderMethod = "addITCondCodeOperands";
409 let PredicateMethod = "isITCondCodeNoAL";
410 let ParserMethod = "parseITCondCode";
412 def pred_noal : Operand<i32> {
413 let PrintMethod = "printMandatoryPredicateOperand";
414 let ParserMatchClass = pred_noal_asmoperand;
415 let DecoderMethod = "DecodePredNoALOperand";
419 // CSEL aliases inverted predicate
420 def pred_noal_inv_asmoperand : AsmOperandClass {
421 let Name = "CondCodeNoALInv";
422 let RenderMethod = "addITCondCodeInvOperands";
423 let PredicateMethod = "isITCondCodeNoAL";
424 let ParserMethod = "parseITCondCode";
426 def pred_noal_inv : Operand<i32> {
427 let PrintMethod = "printMandatoryInvertedPredicateOperand";
428 let ParserMatchClass = pred_noal_inv_asmoperand;
430 //===----------------------------------------------------------------------===//
431 // Multiclass helpers...
435 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
436 string opc, string asm, list<dag> pattern>
437 : T2I<oops, iops, itin, opc, asm, pattern> {
442 let Inst{26} = imm{11};
443 let Inst{14-12} = imm{10-8};
444 let Inst{7-0} = imm{7-0};
448 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
449 string opc, string asm, list<dag> pattern>
450 : T2sI<oops, iops, itin, opc, asm, pattern> {
456 let Inst{26} = imm{11};
457 let Inst{14-12} = imm{10-8};
458 let Inst{7-0} = imm{7-0};
461 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
462 string opc, string asm, list<dag> pattern>
463 : T2I<oops, iops, itin, opc, asm, pattern> {
467 let Inst{19-16} = Rn;
468 let Inst{26} = imm{11};
469 let Inst{14-12} = imm{10-8};
470 let Inst{7-0} = imm{7-0};
474 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
475 string opc, string asm, list<dag> pattern>
476 : T2I<oops, iops, itin, opc, asm, pattern> {
481 let Inst{3-0} = ShiftedRm{3-0};
482 let Inst{5-4} = ShiftedRm{6-5};
483 let Inst{14-12} = ShiftedRm{11-9};
484 let Inst{7-6} = ShiftedRm{8-7};
487 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
488 string opc, string asm, list<dag> pattern>
489 : T2sI<oops, iops, itin, opc, asm, pattern> {
494 let Inst{3-0} = ShiftedRm{3-0};
495 let Inst{5-4} = ShiftedRm{6-5};
496 let Inst{14-12} = ShiftedRm{11-9};
497 let Inst{7-6} = ShiftedRm{8-7};
500 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
501 string opc, string asm, list<dag> pattern>
502 : T2I<oops, iops, itin, opc, asm, pattern> {
506 let Inst{19-16} = Rn;
507 let Inst{3-0} = ShiftedRm{3-0};
508 let Inst{5-4} = ShiftedRm{6-5};
509 let Inst{14-12} = ShiftedRm{11-9};
510 let Inst{7-6} = ShiftedRm{8-7};
513 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
514 string opc, string asm, list<dag> pattern>
515 : T2I<oops, iops, itin, opc, asm, pattern> {
523 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
524 string opc, string asm, list<dag> pattern>
525 : T2sI<oops, iops, itin, opc, asm, pattern> {
533 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
534 string opc, string asm, list<dag> pattern>
535 : T2I<oops, iops, itin, opc, asm, pattern> {
539 let Inst{19-16} = Rn;
544 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
545 string opc, string asm, list<dag> pattern>
546 : T2I<oops, iops, itin, opc, asm, pattern> {
552 let Inst{19-16} = Rn;
553 let Inst{26} = imm{11};
554 let Inst{14-12} = imm{10-8};
555 let Inst{7-0} = imm{7-0};
558 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
559 string opc, string asm, list<dag> pattern>
560 : T2sI<oops, iops, itin, opc, asm, pattern> {
566 let Inst{19-16} = Rn;
567 let Inst{26} = imm{11};
568 let Inst{14-12} = imm{10-8};
569 let Inst{7-0} = imm{7-0};
572 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
573 string opc, string asm, list<dag> pattern>
574 : T2I<oops, iops, itin, opc, asm, pattern> {
581 let Inst{14-12} = imm{4-2};
582 let Inst{7-6} = imm{1-0};
585 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
586 string opc, string asm, list<dag> pattern>
587 : T2sI<oops, iops, itin, opc, asm, pattern> {
594 let Inst{14-12} = imm{4-2};
595 let Inst{7-6} = imm{1-0};
598 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
599 string opc, string asm, list<dag> pattern>
600 : T2I<oops, iops, itin, opc, asm, pattern> {
606 let Inst{19-16} = Rn;
610 class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin,
611 string asm, list<dag> pattern>
612 : T2XI<oops, iops, itin, asm, pattern> {
618 let Inst{19-16} = Rn;
622 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
623 string opc, string asm, list<dag> pattern>
624 : T2sI<oops, iops, itin, opc, asm, pattern> {
630 let Inst{19-16} = Rn;
634 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
635 string opc, string asm, list<dag> pattern>
636 : T2I<oops, iops, itin, opc, asm, pattern> {
642 let Inst{19-16} = Rn;
643 let Inst{3-0} = ShiftedRm{3-0};
644 let Inst{5-4} = ShiftedRm{6-5};
645 let Inst{14-12} = ShiftedRm{11-9};
646 let Inst{7-6} = ShiftedRm{8-7};
649 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
650 string opc, string asm, list<dag> pattern>
651 : T2sI<oops, iops, itin, opc, asm, pattern> {
657 let Inst{19-16} = Rn;
658 let Inst{3-0} = ShiftedRm{3-0};
659 let Inst{5-4} = ShiftedRm{6-5};
660 let Inst{14-12} = ShiftedRm{11-9};
661 let Inst{7-6} = ShiftedRm{8-7};
664 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
665 string opc, string asm, list<dag> pattern>
666 : T2I<oops, iops, itin, opc, asm, pattern> {
672 let Inst{19-16} = Rn;
673 let Inst{15-12} = Ra;
678 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
679 string opc, list<dag> pattern>
680 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
681 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,
682 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]> {
688 let Inst{31-23} = 0b111110111;
689 let Inst{22-20} = opc22_20;
690 let Inst{19-16} = Rn;
691 let Inst{15-12} = RdLo;
692 let Inst{11-8} = RdHi;
693 let Inst{7-4} = opc7_4;
696 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc>
697 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
698 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
699 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
700 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
701 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {
707 let Inst{31-23} = 0b111110111;
708 let Inst{22-20} = opc22_20;
709 let Inst{19-16} = Rn;
710 let Inst{15-12} = RdLo;
711 let Inst{11-8} = RdHi;
712 let Inst{7-4} = opc7_4;
717 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
718 /// binary operation that produces a value. These are predicable and can be
719 /// changed to modify CPSR.
720 multiclass T2I_bin_irs<bits<4> opcod, string opc,
721 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
722 SDPatternOperator opnode, bit Commutable = 0,
725 def ri : T2sTwoRegImm<
726 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
727 opc, "\t$Rd, $Rn, $imm",
728 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
729 Sched<[WriteALU, ReadALU]> {
730 let Inst{31-27} = 0b11110;
732 let Inst{24-21} = opcod;
736 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
737 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
738 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
739 Sched<[WriteALU, ReadALU, ReadALU]> {
740 let isCommutable = Commutable;
741 let Inst{31-27} = 0b11101;
742 let Inst{26-25} = 0b01;
743 let Inst{24-21} = opcod;
745 // In most of these instructions, and most versions of the Arm
746 // architecture, bit 15 of this encoding is listed as (0) rather
747 // than 0, i.e. setting it to 1 is UNPREDICTABLE or a soft-fail
748 // rather than a hard failure. In v8.1-M, this requirement is
749 // upgraded to a hard one for ORR, so that the encodings with 1
750 // in this bit can be reused for other instructions (such as
751 // CSEL). Setting Unpredictable{15} = 1 here would reintroduce
752 // that encoding clash in the auto- generated MC decoder, so I
754 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1);
755 let Inst{14-12} = 0b000; // imm3
756 let Inst{7-6} = 0b00; // imm2
757 let Inst{5-4} = 0b00; // type
760 def rs : T2sTwoRegShiftedReg<
761 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
762 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
763 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
764 Sched<[WriteALUsi, ReadALU]> {
765 let Inst{31-27} = 0b11101;
766 let Inst{26-25} = 0b01;
767 let Inst{24-21} = opcod;
769 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); // see above
771 // Assembly aliases for optional destination operand when it's the same
772 // as the source operand.
773 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
774 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
775 t2_so_imm:$imm, pred:$p,
777 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
778 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
781 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
782 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
783 t2_so_reg:$shift, pred:$p,
787 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
788 // the ".w" suffix to indicate that they are wide.
789 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
790 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
791 SDPatternOperator opnode, bit Commutable = 0> :
792 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
793 // Assembler aliases w/ the ".w" suffix.
794 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
795 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
797 // Assembler aliases w/o the ".w" suffix.
798 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
799 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
801 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
802 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
803 pred:$p, cc_out:$s)>;
805 // and with the optional destination operand, too.
806 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
807 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
808 pred:$p, cc_out:$s)>;
809 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
810 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
812 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
813 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
814 pred:$p, cc_out:$s)>;
817 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
818 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
819 /// it is equivalent to the T2I_bin_irs counterpart.
820 multiclass T2I_rbin_irs<bits<4> opcod, string opc, SDNode opnode> {
822 def ri : T2sTwoRegImm<
823 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
824 opc, ".w\t$Rd, $Rn, $imm",
825 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
826 Sched<[WriteALU, ReadALU]> {
827 let Inst{31-27} = 0b11110;
829 let Inst{24-21} = opcod;
833 def rr : T2sThreeReg<
834 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
835 opc, "\t$Rd, $Rn, $Rm",
836 [/* For disassembly only; pattern left blank */]>,
837 Sched<[WriteALU, ReadALU, ReadALU]> {
838 let Inst{31-27} = 0b11101;
839 let Inst{26-25} = 0b01;
840 let Inst{24-21} = opcod;
841 let Inst{14-12} = 0b000; // imm3
842 let Inst{7-6} = 0b00; // imm2
843 let Inst{5-4} = 0b00; // type
846 def rs : T2sTwoRegShiftedReg<
847 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
848 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
849 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
850 Sched<[WriteALUsi, ReadALU]> {
851 let Inst{31-27} = 0b11101;
852 let Inst{26-25} = 0b01;
853 let Inst{24-21} = opcod;
857 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
858 /// instruction modifies the CPSR register.
860 /// These opcodes will be converted to the real non-S opcodes by
861 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
862 let hasPostISelHook = 1, Defs = [CPSR] in {
863 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
864 InstrItinClass iis, SDNode opnode,
865 bit Commutable = 0> {
867 def ri : t2PseudoInst<(outs rGPR:$Rd),
868 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
870 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
872 Sched<[WriteALU, ReadALU]>;
874 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
876 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
878 Sched<[WriteALU, ReadALU, ReadALU]> {
879 let isCommutable = Commutable;
882 def rs : t2PseudoInst<(outs rGPR:$Rd),
883 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
885 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
886 t2_so_reg:$ShiftedRm))]>,
887 Sched<[WriteALUsi, ReadALUsr]>;
891 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
892 /// operands are reversed.
893 let hasPostISelHook = 1, Defs = [CPSR] in {
894 multiclass T2I_rbin_s_is<SDNode opnode> {
896 def ri : t2PseudoInst<(outs rGPR:$Rd),
897 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
899 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
901 Sched<[WriteALU, ReadALU]>;
903 def rs : t2PseudoInst<(outs rGPR:$Rd),
904 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
906 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
908 Sched<[WriteALUsi, ReadALU]>;
912 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
913 /// patterns for a binary operation that produces a value.
914 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,
915 bit Commutable = 0> {
917 // The register-immediate version is re-materializable. This is useful
918 // in particular for taking the address of a local.
919 let isReMaterializable = 1 in {
920 def ri : T2sTwoRegImm<
921 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
922 opc, ".w\t$Rd, $Rn, $imm",
923 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
924 Sched<[WriteALU, ReadALU]> {
925 let Inst{31-27} = 0b11110;
928 let Inst{23-21} = op23_21;
934 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
935 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
936 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
937 Sched<[WriteALU, ReadALU]> {
941 let Inst{31-27} = 0b11110;
942 let Inst{26} = imm{11};
943 let Inst{25-24} = 0b10;
944 let Inst{23-21} = op23_21;
945 let Inst{20} = 0; // The S bit.
946 let Inst{19-16} = Rn;
948 let Inst{14-12} = imm{10-8};
950 let Inst{7-0} = imm{7-0};
953 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
954 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
955 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
956 Sched<[WriteALU, ReadALU, ReadALU]> {
957 let isCommutable = Commutable;
958 let Inst{31-27} = 0b11101;
959 let Inst{26-25} = 0b01;
961 let Inst{23-21} = op23_21;
962 let Inst{14-12} = 0b000; // imm3
963 let Inst{7-6} = 0b00; // imm2
964 let Inst{5-4} = 0b00; // type
967 def rs : T2sTwoRegShiftedReg<
968 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
969 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
970 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
971 Sched<[WriteALUsi, ReadALU]> {
972 let Inst{31-27} = 0b11101;
973 let Inst{26-25} = 0b01;
975 let Inst{23-21} = op23_21;
979 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
980 /// for a binary operation that produces a value and use the carry
981 /// bit. It's not predicable.
982 let Defs = [CPSR], Uses = [CPSR] in {
983 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
984 bit Commutable = 0> {
986 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
987 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
988 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
989 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
990 let Inst{31-27} = 0b11110;
992 let Inst{24-21} = opcod;
996 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
997 opc, ".w\t$Rd, $Rn, $Rm",
998 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
999 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
1000 let isCommutable = Commutable;
1001 let Inst{31-27} = 0b11101;
1002 let Inst{26-25} = 0b01;
1003 let Inst{24-21} = opcod;
1004 let Inst{14-12} = 0b000; // imm3
1005 let Inst{7-6} = 0b00; // imm2
1006 let Inst{5-4} = 0b00; // type
1009 def rs : T2sTwoRegShiftedReg<
1010 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
1011 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
1012 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
1013 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
1014 let Inst{31-27} = 0b11101;
1015 let Inst{26-25} = 0b01;
1016 let Inst{24-21} = opcod;
1021 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
1022 // rotate operation that produces a value.
1023 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> {
1025 def ri : T2sTwoRegShiftImm<
1026 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
1027 opc, ".w\t$Rd, $Rm, $imm",
1028 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
1030 let Inst{31-27} = 0b11101;
1031 let Inst{26-21} = 0b010010;
1032 let Inst{19-16} = 0b1111; // Rn
1034 let Inst{5-4} = opcod;
1037 def rr : T2sThreeReg<
1038 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
1039 opc, ".w\t$Rd, $Rn, $Rm",
1040 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1042 let Inst{31-27} = 0b11111;
1043 let Inst{26-23} = 0b0100;
1044 let Inst{22-21} = opcod;
1045 let Inst{15-12} = 0b1111;
1046 let Inst{7-4} = 0b0000;
1049 // Optional destination register
1050 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
1051 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
1053 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
1054 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
1057 // Assembler aliases w/o the ".w" suffix.
1058 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
1059 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
1061 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
1062 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
1065 // and with the optional destination operand, too.
1066 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
1067 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
1069 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
1070 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
1074 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1075 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
1076 /// a explicit result, only implicitly set CPSR.
1077 multiclass T2I_cmp_irs<bits<4> opcod, string opc, RegisterClass LHSGPR,
1078 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1079 SDPatternOperator opnode> {
1080 let isCompare = 1, Defs = [CPSR] in {
1082 def ri : T2OneRegCmpImm<
1083 (outs), (ins LHSGPR:$Rn, t2_so_imm:$imm), iii,
1084 opc, ".w\t$Rn, $imm",
1085 [(opnode LHSGPR:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
1086 let Inst{31-27} = 0b11110;
1088 let Inst{24-21} = opcod;
1089 let Inst{20} = 1; // The S bit.
1091 let Inst{11-8} = 0b1111; // Rd
1094 def rr : T2TwoRegCmp<
1095 (outs), (ins LHSGPR:$Rn, rGPR:$Rm), iir,
1096 opc, ".w\t$Rn, $Rm",
1097 [(opnode LHSGPR:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
1098 let Inst{31-27} = 0b11101;
1099 let Inst{26-25} = 0b01;
1100 let Inst{24-21} = opcod;
1101 let Inst{20} = 1; // The S bit.
1102 let Inst{14-12} = 0b000; // imm3
1103 let Inst{11-8} = 0b1111; // Rd
1104 let Inst{7-6} = 0b00; // imm2
1105 let Inst{5-4} = 0b00; // type
1108 def rs : T2OneRegCmpShiftedReg<
1109 (outs), (ins LHSGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
1110 opc, ".w\t$Rn, $ShiftedRm",
1111 [(opnode LHSGPR:$Rn, t2_so_reg:$ShiftedRm)]>,
1112 Sched<[WriteCMPsi]> {
1113 let Inst{31-27} = 0b11101;
1114 let Inst{26-25} = 0b01;
1115 let Inst{24-21} = opcod;
1116 let Inst{20} = 1; // The S bit.
1117 let Inst{11-8} = 0b1111; // Rd
1121 // Assembler aliases w/o the ".w" suffix.
1122 // No alias here for 'rr' version as not all instantiations of this
1123 // multiclass want one (CMP in particular, does not).
1124 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
1125 (!cast<Instruction>(NAME#"ri") LHSGPR:$Rn, t2_so_imm:$imm, pred:$p)>;
1126 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
1127 (!cast<Instruction>(NAME#"rs") LHSGPR:$Rn, t2_so_reg:$shift, pred:$p)>;
1130 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
1131 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
1132 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1134 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
1135 opc, ".w\t$Rt, $addr",
1136 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,
1140 let Inst{31-25} = 0b1111100;
1141 let Inst{24} = signed;
1143 let Inst{22-21} = opcod;
1144 let Inst{20} = 1; // load
1145 let Inst{19-16} = addr{16-13}; // Rn
1146 let Inst{15-12} = Rt;
1147 let Inst{11-0} = addr{11-0}; // imm
1149 let DecoderMethod = "DecodeT2LoadImm12";
1151 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
1152 opc, "\t$Rt, $addr",
1153 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>,
1157 let Inst{31-27} = 0b11111;
1158 let Inst{26-25} = 0b00;
1159 let Inst{24} = signed;
1161 let Inst{22-21} = opcod;
1162 let Inst{20} = 1; // load
1163 let Inst{19-16} = addr{12-9}; // Rn
1164 let Inst{15-12} = Rt;
1166 // Offset: index==TRUE, wback==FALSE
1167 let Inst{10} = 1; // The P bit.
1168 let Inst{9} = addr{8}; // U
1169 let Inst{8} = 0; // The W bit.
1170 let Inst{7-0} = addr{7-0}; // imm
1172 let DecoderMethod = "DecodeT2LoadImm8";
1174 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
1175 opc, ".w\t$Rt, $addr",
1176 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]>,
1178 let Inst{31-27} = 0b11111;
1179 let Inst{26-25} = 0b00;
1180 let Inst{24} = signed;
1182 let Inst{22-21} = opcod;
1183 let Inst{20} = 1; // load
1184 let Inst{11-6} = 0b000000;
1187 let Inst{15-12} = Rt;
1190 let Inst{19-16} = addr{9-6}; // Rn
1191 let Inst{3-0} = addr{5-2}; // Rm
1192 let Inst{5-4} = addr{1-0}; // imm
1194 let DecoderMethod = "DecodeT2LoadShift";
1197 // pci variant is very similar to i12, but supports negative offsets
1199 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1200 opc, ".w\t$Rt, $addr",
1201 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>,
1203 let isReMaterializable = 1;
1204 let Inst{31-27} = 0b11111;
1205 let Inst{26-25} = 0b00;
1206 let Inst{24} = signed;
1207 let Inst{22-21} = opcod;
1208 let Inst{20} = 1; // load
1209 let Inst{19-16} = 0b1111; // Rn
1212 let Inst{15-12} = Rt{3-0};
1215 let Inst{23} = addr{12}; // add = (U == '1')
1216 let Inst{11-0} = addr{11-0};
1218 let DecoderMethod = "DecodeT2LoadLabel";
1222 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1223 multiclass T2I_st<bits<2> opcod, string opc,
1224 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1226 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1227 opc, ".w\t$Rt, $addr",
1228 [(opnode target:$Rt, t2addrmode_imm12:$addr)]>,
1230 let Inst{31-27} = 0b11111;
1231 let Inst{26-23} = 0b0001;
1232 let Inst{22-21} = opcod;
1233 let Inst{20} = 0; // !load
1236 let Inst{15-12} = Rt;
1239 let addr{12} = 1; // add = TRUE
1240 let Inst{19-16} = addr{16-13}; // Rn
1241 let Inst{23} = addr{12}; // U
1242 let Inst{11-0} = addr{11-0}; // imm
1244 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1245 opc, "\t$Rt, $addr",
1246 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]>,
1248 let Inst{31-27} = 0b11111;
1249 let Inst{26-23} = 0b0000;
1250 let Inst{22-21} = opcod;
1251 let Inst{20} = 0; // !load
1253 // Offset: index==TRUE, wback==FALSE
1254 let Inst{10} = 1; // The P bit.
1255 let Inst{8} = 0; // The W bit.
1258 let Inst{15-12} = Rt;
1261 let Inst{19-16} = addr{12-9}; // Rn
1262 let Inst{9} = addr{8}; // U
1263 let Inst{7-0} = addr{7-0}; // imm
1265 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1266 opc, ".w\t$Rt, $addr",
1267 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]>,
1269 let Inst{31-27} = 0b11111;
1270 let Inst{26-23} = 0b0000;
1271 let Inst{22-21} = opcod;
1272 let Inst{20} = 0; // !load
1273 let Inst{11-6} = 0b000000;
1276 let Inst{15-12} = Rt;
1279 let Inst{19-16} = addr{9-6}; // Rn
1280 let Inst{3-0} = addr{5-2}; // Rm
1281 let Inst{5-4} = addr{1-0}; // imm
1285 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1286 /// register and one whose operand is a register rotated by 8/16/24.
1287 class T2I_ext_rrot_base<bits<3> opcod, dag iops, dag oops,
1288 string opc, string oprs,
1290 : T2TwoReg<iops, oops, IIC_iEXTr, opc, oprs, pattern> {
1292 let Inst{31-27} = 0b11111;
1293 let Inst{26-23} = 0b0100;
1294 let Inst{22-20} = opcod;
1295 let Inst{19-16} = 0b1111; // Rn
1296 let Inst{15-12} = 0b1111;
1298 let Inst{5-4} = rot; // rotate
1301 class T2I_ext_rrot<bits<3> opcod, string opc>
1302 : T2I_ext_rrot_base<opcod,
1304 (ins rGPR:$Rm, rot_imm:$rot),
1305 opc, ".w\t$Rd, $Rm$rot", []>,
1306 Requires<[IsThumb2]>,
1307 Sched<[WriteALU, ReadALU]>;
1309 // UXTB16, SXTB16 - Requires HasDSP, does not need the .w qualifier.
1310 class T2I_ext_rrot_xtb16<bits<3> opcod, string opc>
1311 : T2I_ext_rrot_base<opcod,
1313 (ins rGPR:$Rm, rot_imm:$rot),
1314 opc, "\t$Rd, $Rm$rot", []>,
1315 Requires<[HasDSP, IsThumb2]>,
1316 Sched<[WriteALU, ReadALU]>;
1318 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1319 /// register and one whose operand is a register rotated by 8/16/24.
1320 class T2I_exta_rrot<bits<3> opcod, string opc>
1321 : T2ThreeReg<(outs rGPR:$Rd),
1322 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1323 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1324 Requires<[HasDSP, IsThumb2]>,
1325 Sched<[WriteALU, ReadALU]> {
1327 let Inst{31-27} = 0b11111;
1328 let Inst{26-23} = 0b0100;
1329 let Inst{22-20} = opcod;
1330 let Inst{15-12} = 0b1111;
1332 let Inst{5-4} = rot;
1335 //===----------------------------------------------------------------------===//
1337 //===----------------------------------------------------------------------===//
1339 //===----------------------------------------------------------------------===//
1340 // Miscellaneous Instructions.
1343 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1344 string asm, list<dag> pattern>
1345 : T2XI<oops, iops, itin, asm, pattern> {
1349 let Inst{11-8} = Rd;
1350 let Inst{26} = label{11};
1351 let Inst{14-12} = label{10-8};
1352 let Inst{7-0} = label{7-0};
1355 // LEApcrel - Load a pc-relative address into a register without offending the
1357 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1358 (ins t2adrlabel:$addr, pred:$p),
1359 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1360 Sched<[WriteALU, ReadALU]> {
1361 let Inst{31-27} = 0b11110;
1362 let Inst{25-24} = 0b10;
1363 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1366 let Inst{19-16} = 0b1111; // Rn
1371 let Inst{11-8} = Rd;
1372 let Inst{23} = addr{12};
1373 let Inst{21} = addr{12};
1374 let Inst{26} = addr{11};
1375 let Inst{14-12} = addr{10-8};
1376 let Inst{7-0} = addr{7-0};
1378 let DecoderMethod = "DecodeT2Adr";
1381 let hasSideEffects = 0, isReMaterializable = 1 in
1382 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1383 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1384 let hasSideEffects = 1 in
1385 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1386 (ins i32imm:$label, pred:$p),
1388 []>, Sched<[WriteALU, ReadALU]>;
1391 //===----------------------------------------------------------------------===//
1392 // Load / store Instructions.
1396 let canFoldAsLoad = 1, isReMaterializable = 1 in
1397 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>;
1399 // Loads with zero extension
1400 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1401 GPRnopc, zextloadi16>;
1402 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1403 GPRnopc, zextloadi8>;
1405 // Loads with sign extension
1406 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1407 GPRnopc, sextloadi16>;
1408 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1409 GPRnopc, sextloadi8>;
1411 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1413 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1414 (ins t2addrmode_imm8s4:$addr),
1415 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>,
1417 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1419 // zextload i1 -> zextload i8
1420 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1421 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1422 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1423 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1424 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1425 (t2LDRBs t2addrmode_so_reg:$addr)>;
1426 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1427 (t2LDRBpci tconstpool:$addr)>;
1429 // extload -> zextload
1430 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1432 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1433 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1434 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1435 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1436 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1437 (t2LDRBs t2addrmode_so_reg:$addr)>;
1438 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1439 (t2LDRBpci tconstpool:$addr)>;
1441 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1442 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1443 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1444 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1445 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1446 (t2LDRBs t2addrmode_so_reg:$addr)>;
1447 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1448 (t2LDRBpci tconstpool:$addr)>;
1450 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1451 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1452 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1453 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1454 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1455 (t2LDRHs t2addrmode_so_reg:$addr)>;
1456 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1457 (t2LDRHpci tconstpool:$addr)>;
1459 // FIXME: The destination register of the loads and stores can't be PC, but
1460 // can be SP. We need another regclass (similar to rGPR) to represent
1461 // that. Not a pressing issue since these are selected manually,
1466 let mayLoad = 1, hasSideEffects = 0 in {
1467 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1468 (ins t2addrmode_imm8_pre:$addr),
1469 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1470 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1473 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1474 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1475 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1476 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1479 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1480 (ins t2addrmode_imm8_pre:$addr),
1481 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1482 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1485 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1486 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1487 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1488 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1491 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1492 (ins t2addrmode_imm8_pre:$addr),
1493 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1494 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1497 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1498 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1499 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1500 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1503 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1504 (ins t2addrmode_imm8_pre:$addr),
1505 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1506 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1507 []>, Sched<[WriteLd]>;
1509 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1510 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1511 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1512 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1515 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1516 (ins t2addrmode_imm8_pre:$addr),
1517 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1518 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1519 []>, Sched<[WriteLd]>;
1521 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1522 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1523 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1524 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1526 } // mayLoad = 1, hasSideEffects = 0
1528 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1529 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1530 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1531 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1532 "\t$Rt, $addr", []>, Sched<[WriteLd]> {
1535 let Inst{31-27} = 0b11111;
1536 let Inst{26-25} = 0b00;
1537 let Inst{24} = signed;
1539 let Inst{22-21} = type;
1540 let Inst{20} = 1; // load
1541 let Inst{19-16} = addr{12-9};
1542 let Inst{15-12} = Rt;
1544 let Inst{10-8} = 0b110; // PUW.
1545 let Inst{7-0} = addr{7-0};
1547 let DecoderMethod = "DecodeT2LoadT";
1550 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1551 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1552 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1553 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1554 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1556 class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,
1557 string opc, string asm, list<dag> pattern>
1558 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,
1559 opc, asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {
1563 let Inst{31-27} = 0b11101;
1564 let Inst{26-24} = 0b000;
1565 let Inst{23-20} = bits23_20;
1566 let Inst{11-6} = 0b111110;
1567 let Inst{5-4} = bit54;
1568 let Inst{3-0} = 0b1111;
1570 // Encode instruction operands
1571 let Inst{19-16} = addr;
1572 let Inst{15-12} = Rt;
1575 def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),
1576 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>,
1578 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1579 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>,
1581 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
1582 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>,
1586 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, store>;
1587 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1588 rGPR, truncstorei8>;
1589 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1590 rGPR, truncstorei16>;
1593 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
1594 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1595 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1596 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>,
1601 let mayStore = 1, hasSideEffects = 0 in {
1602 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1603 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
1604 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1605 "str", "\t$Rt, $addr!",
1606 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1609 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1610 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1611 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1612 "strh", "\t$Rt, $addr!",
1613 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1616 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1617 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1618 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1619 "strb", "\t$Rt, $addr!",
1620 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1622 } // mayStore = 1, hasSideEffects = 0
1624 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1625 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1626 t2am_imm8_offset:$offset),
1627 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1628 "str", "\t$Rt, $Rn$offset",
1629 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1630 [(set GPRnopc:$Rn_wb,
1631 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1632 t2am_imm8_offset:$offset))]>,
1635 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1636 (ins rGPR:$Rt, addr_offset_none:$Rn,
1637 t2am_imm8_offset:$offset),
1638 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1639 "strh", "\t$Rt, $Rn$offset",
1640 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1641 [(set GPRnopc:$Rn_wb,
1642 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1643 t2am_imm8_offset:$offset))]>,
1646 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1647 (ins rGPR:$Rt, addr_offset_none:$Rn,
1648 t2am_imm8_offset:$offset),
1649 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1650 "strb", "\t$Rt, $Rn$offset",
1651 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1652 [(set GPRnopc:$Rn_wb,
1653 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1654 t2am_imm8_offset:$offset))]>,
1657 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1658 // put the patterns on the instruction definitions directly as ISel wants
1659 // the address base and offset to be separate operands, not a single
1660 // complex operand like we represent the instructions themselves. The
1661 // pseudos map between the two.
1662 let usesCustomInserter = 1,
1663 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1664 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1665 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1667 [(set GPRnopc:$Rn_wb,
1668 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
1670 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1671 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1673 [(set GPRnopc:$Rn_wb,
1674 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
1676 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1677 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1679 [(set GPRnopc:$Rn_wb,
1680 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
1684 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1686 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1687 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1688 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1689 "\t$Rt, $addr", []>, Sched<[WriteST]> {
1690 let Inst{31-27} = 0b11111;
1691 let Inst{26-25} = 0b00;
1692 let Inst{24} = 0; // not signed
1694 let Inst{22-21} = type;
1695 let Inst{20} = 0; // store
1697 let Inst{10-8} = 0b110; // PUW
1701 let Inst{15-12} = Rt;
1702 let Inst{19-16} = addr{12-9};
1703 let Inst{7-0} = addr{7-0};
1706 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1707 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1708 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1710 // ldrd / strd pre / post variants
1713 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1714 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
1715 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
1717 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1721 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1722 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1723 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1724 "$addr.base = $wb", []>, Sched<[WriteLd]>;
1727 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1728 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1729 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1730 "$addr.base = $wb", []>, Sched<[WriteST]> {
1731 let DecoderMethod = "DecodeT2STRDPreInstruction";
1735 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1736 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1737 t2am_imm8s4_offset:$imm),
1738 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1739 "$addr.base = $wb", []>, Sched<[WriteST]>;
1741 class T2Istrrel<bits<2> bit54, dag oops, dag iops,
1742 string opc, string asm, list<dag> pattern>
1743 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,
1744 asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]>,
1749 let Inst{31-27} = 0b11101;
1750 let Inst{26-20} = 0b0001100;
1751 let Inst{11-6} = 0b111110;
1752 let Inst{5-4} = bit54;
1753 let Inst{3-0} = 0b1111;
1755 // Encode instruction operands
1756 let Inst{19-16} = addr;
1757 let Inst{15-12} = Rt;
1760 def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1761 "stl", "\t$Rt, $addr", []>;
1762 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1763 "stlb", "\t$Rt, $addr", []>;
1764 def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1765 "stlh", "\t$Rt, $addr", []>;
1767 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1768 // data/instruction access.
1769 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1770 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1771 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1773 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1775 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1776 Sched<[WritePreLd]> {
1777 let Inst{31-25} = 0b1111100;
1778 let Inst{24} = instr;
1781 let Inst{21} = write;
1783 let Inst{15-12} = 0b1111;
1786 let Inst{19-16} = addr{16-13}; // Rn
1787 let Inst{11-0} = addr{11-0}; // imm12
1789 let DecoderMethod = "DecodeT2LoadImm12";
1792 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1794 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1795 Sched<[WritePreLd]> {
1796 let Inst{31-25} = 0b1111100;
1797 let Inst{24} = instr;
1798 let Inst{23} = 0; // U = 0
1800 let Inst{21} = write;
1802 let Inst{15-12} = 0b1111;
1803 let Inst{11-8} = 0b1100;
1806 let Inst{19-16} = addr{12-9}; // Rn
1807 let Inst{7-0} = addr{7-0}; // imm8
1809 let DecoderMethod = "DecodeT2LoadImm8";
1812 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1814 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1815 Sched<[WritePreLd]> {
1816 let Inst{31-25} = 0b1111100;
1817 let Inst{24} = instr;
1818 let Inst{23} = 0; // add = TRUE for T1
1820 let Inst{21} = write;
1822 let Inst{15-12} = 0b1111;
1823 let Inst{11-6} = 0b000000;
1826 let Inst{19-16} = addr{9-6}; // Rn
1827 let Inst{3-0} = addr{5-2}; // Rm
1828 let Inst{5-4} = addr{1-0}; // imm2
1830 let DecoderMethod = "DecodeT2LoadShift";
1834 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1835 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1836 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1838 // pci variant is very similar to i12, but supports negative offsets
1839 // from the PC. Only PLD and PLI have pci variants (not PLDW)
1840 class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
1841 IIC_Preload, opc, "\t$addr",
1842 [(ARMPreload (ARMWrapper tconstpool:$addr),
1843 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
1844 let Inst{31-25} = 0b1111100;
1845 let Inst{24} = inst;
1846 let Inst{22-20} = 0b001;
1847 let Inst{19-16} = 0b1111;
1848 let Inst{15-12} = 0b1111;
1851 let Inst{23} = addr{12}; // add = (U == '1')
1852 let Inst{11-0} = addr{11-0}; // imm12
1854 let DecoderMethod = "DecodeT2LoadLabel";
1857 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1858 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
1860 //===----------------------------------------------------------------------===//
1861 // Load / store multiple Instructions.
1864 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1865 InstrItinClass itin_upd, bit L_bit> {
1867 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1868 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1872 let Inst{31-27} = 0b11101;
1873 let Inst{26-25} = 0b00;
1874 let Inst{24-23} = 0b01; // Increment After
1876 let Inst{21} = 0; // No writeback
1877 let Inst{20} = L_bit;
1878 let Inst{19-16} = Rn;
1879 let Inst{15-0} = regs;
1882 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1883 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1887 let Inst{31-27} = 0b11101;
1888 let Inst{26-25} = 0b00;
1889 let Inst{24-23} = 0b01; // Increment After
1891 let Inst{21} = 1; // Writeback
1892 let Inst{20} = L_bit;
1893 let Inst{19-16} = Rn;
1894 let Inst{15-0} = regs;
1897 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1898 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1902 let Inst{31-27} = 0b11101;
1903 let Inst{26-25} = 0b00;
1904 let Inst{24-23} = 0b10; // Decrement Before
1906 let Inst{21} = 0; // No writeback
1907 let Inst{20} = L_bit;
1908 let Inst{19-16} = Rn;
1909 let Inst{15-0} = regs;
1912 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1913 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1917 let Inst{31-27} = 0b11101;
1918 let Inst{26-25} = 0b00;
1919 let Inst{24-23} = 0b10; // Decrement Before
1921 let Inst{21} = 1; // Writeback
1922 let Inst{20} = L_bit;
1923 let Inst{19-16} = Rn;
1924 let Inst{15-0} = regs;
1928 let hasSideEffects = 0 in {
1930 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
1931 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1933 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1934 InstrItinClass itin_upd, bit L_bit> {
1936 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1937 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1941 let Inst{31-27} = 0b11101;
1942 let Inst{26-25} = 0b00;
1943 let Inst{24-23} = 0b01; // Increment After
1945 let Inst{21} = 0; // No writeback
1946 let Inst{20} = L_bit;
1947 let Inst{19-16} = Rn;
1949 let Inst{14} = regs{14};
1951 let Inst{12-0} = regs{12-0};
1954 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1955 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1959 let Inst{31-27} = 0b11101;
1960 let Inst{26-25} = 0b00;
1961 let Inst{24-23} = 0b01; // Increment After
1963 let Inst{21} = 1; // Writeback
1964 let Inst{20} = L_bit;
1965 let Inst{19-16} = Rn;
1967 let Inst{14} = regs{14};
1969 let Inst{12-0} = regs{12-0};
1972 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1973 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1977 let Inst{31-27} = 0b11101;
1978 let Inst{26-25} = 0b00;
1979 let Inst{24-23} = 0b10; // Decrement Before
1981 let Inst{21} = 0; // No writeback
1982 let Inst{20} = L_bit;
1983 let Inst{19-16} = Rn;
1985 let Inst{14} = regs{14};
1987 let Inst{12-0} = regs{12-0};
1990 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1991 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1995 let Inst{31-27} = 0b11101;
1996 let Inst{26-25} = 0b00;
1997 let Inst{24-23} = 0b10; // Decrement Before
1999 let Inst{21} = 1; // Writeback
2000 let Inst{20} = L_bit;
2001 let Inst{19-16} = Rn;
2003 let Inst{14} = regs{14};
2005 let Inst{12-0} = regs{12-0};
2010 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2011 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
2016 //===----------------------------------------------------------------------===//
2017 // Move Instructions.
2020 let hasSideEffects = 0 in
2021 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr,
2022 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
2023 let Inst{31-27} = 0b11101;
2024 let Inst{26-25} = 0b01;
2025 let Inst{24-21} = 0b0010;
2026 let Inst{19-16} = 0b1111; // Rn
2028 let Inst{14-12} = 0b000;
2029 let Inst{7-4} = 0b0000;
2031 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2032 pred:$p, zero_reg)>;
2033 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2035 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2038 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
2039 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
2040 AddedComplexity = 1 in
2041 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
2042 "mov", ".w\t$Rd, $imm",
2043 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
2044 let Inst{31-27} = 0b11110;
2046 let Inst{24-21} = 0b0010;
2047 let Inst{19-16} = 0b1111; // Rn
2051 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
2052 // Use aliases to get that to play nice here.
2053 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2055 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2058 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2059 pred:$p, zero_reg)>;
2060 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2061 pred:$p, zero_reg)>;
2063 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2064 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
2065 "movw", "\t$Rd, $imm",
2066 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,
2067 Requires<[IsThumb, HasV8MBaseline]> {
2068 let Inst{31-27} = 0b11110;
2070 let Inst{24-21} = 0b0010;
2071 let Inst{20} = 0; // The S bit.
2077 let Inst{11-8} = Rd;
2078 let Inst{19-16} = imm{15-12};
2079 let Inst{26} = imm{11};
2080 let Inst{14-12} = imm{10-8};
2081 let Inst{7-0} = imm{7-0};
2082 let DecoderMethod = "DecodeT2MOVTWInstruction";
2085 def : InstAlias<"mov${p} $Rd, $imm",
2086 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
2087 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteALU]>;
2089 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
2090 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
2093 let Constraints = "$src = $Rd" in {
2094 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
2095 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
2096 "movt", "\t$Rd, $imm",
2098 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
2100 Requires<[IsThumb, HasV8MBaseline]> {
2101 let Inst{31-27} = 0b11110;
2103 let Inst{24-21} = 0b0110;
2104 let Inst{20} = 0; // The S bit.
2110 let Inst{11-8} = Rd;
2111 let Inst{19-16} = imm{15-12};
2112 let Inst{26} = imm{11};
2113 let Inst{14-12} = imm{10-8};
2114 let Inst{7-0} = imm{7-0};
2115 let DecoderMethod = "DecodeT2MOVTWInstruction";
2118 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
2119 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
2120 Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;
2123 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
2125 //===----------------------------------------------------------------------===//
2126 // Extend Instructions.
2131 def t2SXTB : T2I_ext_rrot<0b100, "sxtb">;
2132 def t2SXTH : T2I_ext_rrot<0b000, "sxth">;
2133 def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">;
2135 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab">;
2136 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">;
2137 def t2SXTAB16 : T2I_exta_rrot<0b010, "sxtab16">;
2139 def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i8),
2140 (t2SXTB rGPR:$Rn, rot_imm:$rot)>;
2141 def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i16),
2142 (t2SXTH rGPR:$Rn, rot_imm:$rot)>;
2143 def : Thumb2DSPPat<(add rGPR:$Rn,
2144 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i8)),
2145 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2146 def : Thumb2DSPPat<(add rGPR:$Rn,
2147 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i16)),
2148 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2149 def : Thumb2DSPPat<(int_arm_sxtb16 rGPR:$Rn),
2150 (t2SXTB16 rGPR:$Rn, 0)>;
2151 def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, rGPR:$Rm),
2152 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>;
2153 def : Thumb2DSPPat<(int_arm_sxtb16 (rotr rGPR:$Rn, rot_imm:$rot)),
2154 (t2SXTB16 rGPR:$Rn, rot_imm:$rot)>;
2155 def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)),
2156 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2159 // A simple right-shift can also be used in most cases (the exception is the
2160 // SXTH operations with a rotate of 24: there the non-contiguous bits are
2162 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2163 (srl rGPR:$Rm, rot_imm:$rot), i8)),
2164 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2165 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2166 (srl rGPR:$Rm, imm8_or_16:$rot), i16)),
2167 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2168 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2169 (rotr rGPR:$Rm, (i32 24)), i16)),
2170 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
2171 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2172 (or (srl rGPR:$Rm, (i32 24)),
2173 (shl rGPR:$Rm, (i32 8))), i16)),
2174 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
2178 let AddedComplexity = 16 in {
2179 def t2UXTB : T2I_ext_rrot<0b101, "uxtb">;
2180 def t2UXTH : T2I_ext_rrot<0b001, "uxth">;
2181 def t2UXTB16 : T2I_ext_rrot_xtb16<0b011, "uxtb16">;
2183 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x000000FF),
2184 (t2UXTB rGPR:$Rm, rot_imm:$rot)>;
2185 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x0000FFFF),
2186 (t2UXTH rGPR:$Rm, rot_imm:$rot)>;
2187 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF),
2188 (t2UXTB16 rGPR:$Rm, rot_imm:$rot)>;
2190 def : Thumb2DSPPat<(int_arm_uxtb16 rGPR:$Rm),
2191 (t2UXTB16 rGPR:$Rm, 0)>;
2192 def : Thumb2DSPPat<(int_arm_uxtb16 (rotr rGPR:$Rn, rot_imm:$rot)),
2193 (t2UXTB16 rGPR:$Rn, rot_imm:$rot)>;
2195 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2196 // The transformation should probably be done as a combiner action
2197 // instead so we can include a check for masking back in the upper
2198 // eight bits of the source into the lower eight bits of the result.
2199 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
2200 // (t2UXTB16 rGPR:$Src, 3)>,
2201 // Requires<[HasDSP, IsThumb2]>;
2202 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
2203 (t2UXTB16 rGPR:$Src, 1)>,
2204 Requires<[HasDSP, IsThumb2]>;
2206 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab">;
2207 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah">;
2208 def t2UXTAB16 : T2I_exta_rrot<0b011, "uxtab16">;
2210 def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),
2212 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2213 def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),
2215 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2216 def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot),
2218 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2219 def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot),
2221 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2222 def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, rGPR:$Rm),
2223 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>;
2224 def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)),
2225 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2229 //===----------------------------------------------------------------------===//
2230 // Arithmetic Instructions.
2234 defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
2235 defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
2237 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
2239 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
2240 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
2241 // AdjustInstrPostInstrSelection where we determine whether or not to
2242 // set the "s" bit based on CPSR liveness.
2244 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
2245 // support for an optional CPSR definition that corresponds to the DAG
2246 // node's second value. We can then eliminate the implicit def of CPSR.
2247 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>;
2248 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>;
2250 def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_imm:$imm),
2251 (t2SUBSri $Rn, t2_so_imm:$imm)>;
2252 def : T2Pat<(ARMsubs GPRnopc:$Rn, rGPR:$Rm), (t2SUBSrr $Rn, $Rm)>;
2253 def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
2254 (t2SUBSrs $Rn, t2_so_reg:$ShiftedRm)>;
2256 let hasPostISelHook = 1 in {
2257 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1>;
2258 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube>;
2261 def : t2InstSubst<"adc${s}${p} $rd, $rn, $imm",
2262 (t2SBCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
2263 def : t2InstSubst<"sbc${s}${p} $rd, $rn, $imm",
2264 (t2ADCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
2266 def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",
2267 (t2SUBri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
2268 def : t2InstSubst<"addw${p} $rd, $rn, $imm",
2269 (t2SUBri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
2270 def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",
2271 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
2272 def : t2InstSubst<"subw${p} $rd, $rn, $imm",
2273 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
2274 def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
2275 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
2276 def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm",
2277 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
2278 def : t2InstSubst<"sub${p} $rd, $rn, $imm",
2279 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
2281 defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>;
2283 // FIXME: Eliminate them if we can write def : Pat patterns which defines
2284 // CPSR and the implicit def of CPSR is not needed.
2285 defm t2RSBS : T2I_rbin_s_is <ARMsubc>;
2287 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2288 // The assume-no-carry-in form uses the negation of the input since add/sub
2289 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2290 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2292 // The AddedComplexity preferences the first variant over the others since
2293 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
2294 let AddedComplexity = 1 in
2295 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
2296 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
2297 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
2298 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
2299 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
2300 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
2301 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
2302 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2304 // Do the same for v8m targets since they support movw with a 16-bit value.
2305 def : T1Pat<(add tGPR:$src, imm0_65535_neg:$imm),
2306 (tSUBrr tGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>,
2307 Requires<[HasV8MBaseline]>;
2309 let AddedComplexity = 1 in
2310 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
2311 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
2312 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
2313 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
2314 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
2315 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2316 // The with-carry-in form matches bitwise not instead of the negation.
2317 // Effectively, the inverse interpretation of the carry flag already accounts
2318 // for part of the negation.
2319 let AddedComplexity = 1 in
2320 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
2321 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
2322 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
2323 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
2324 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
2325 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
2327 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2328 NoItinerary, "sel", "\t$Rd, $Rn, $Rm",
2329 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2330 Requires<[IsThumb2, HasDSP]> {
2331 let Inst{31-27} = 0b11111;
2332 let Inst{26-24} = 0b010;
2334 let Inst{22-20} = 0b010;
2335 let Inst{15-12} = 0b1111;
2337 let Inst{6-4} = 0b000;
2340 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
2341 // And Miscellaneous operations -- for disassembly only
2342 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2343 list<dag> pat, dag iops, string asm>
2344 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2345 Requires<[IsThumb2, HasDSP]> {
2346 let Inst{31-27} = 0b11111;
2347 let Inst{26-23} = 0b0101;
2348 let Inst{22-20} = op22_20;
2349 let Inst{15-12} = 0b1111;
2350 let Inst{7-4} = op7_4;
2356 let Inst{11-8} = Rd;
2357 let Inst{19-16} = Rn;
2361 class T2I_pam_intrinsics<bits<3> op22_20, bits<4> op7_4, string opc,
2362 Intrinsic intrinsic>
2363 : T2I_pam<op22_20, op7_4, opc,
2364 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))],
2365 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">;
2367 class T2I_pam_intrinsics_rev<bits<3> op22_20, bits<4> op7_4, string opc>
2368 : T2I_pam<op22_20, op7_4, opc, [],
2369 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2371 // Saturating add/subtract
2372 def t2QADD16 : T2I_pam_intrinsics<0b001, 0b0001, "qadd16", int_arm_qadd16>;
2373 def t2QADD8 : T2I_pam_intrinsics<0b000, 0b0001, "qadd8", int_arm_qadd8>;
2374 def t2QASX : T2I_pam_intrinsics<0b010, 0b0001, "qasx", int_arm_qasx>;
2375 def t2UQSUB8 : T2I_pam_intrinsics<0b100, 0b0101, "uqsub8", int_arm_uqsub8>;
2376 def t2QSAX : T2I_pam_intrinsics<0b110, 0b0001, "qsax", int_arm_qsax>;
2377 def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>;
2378 def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>;
2379 def t2UQADD16 : T2I_pam_intrinsics<0b001, 0b0101, "uqadd16", int_arm_uqadd16>;
2380 def t2UQADD8 : T2I_pam_intrinsics<0b000, 0b0101, "uqadd8", int_arm_uqadd8>;
2381 def t2UQASX : T2I_pam_intrinsics<0b010, 0b0101, "uqasx", int_arm_uqasx>;
2382 def t2UQSAX : T2I_pam_intrinsics<0b110, 0b0101, "uqsax", int_arm_uqsax>;
2383 def t2UQSUB16 : T2I_pam_intrinsics<0b101, 0b0101, "uqsub16", int_arm_uqsub16>;
2384 def t2QADD : T2I_pam_intrinsics_rev<0b000, 0b1000, "qadd">;
2385 def t2QSUB : T2I_pam_intrinsics_rev<0b000, 0b1010, "qsub">;
2386 def t2QDADD : T2I_pam_intrinsics_rev<0b000, 0b1001, "qdadd">;
2387 def t2QDSUB : T2I_pam_intrinsics_rev<0b000, 0b1011, "qdsub">;
2389 def : Thumb2DSPPat<(int_arm_qadd rGPR:$Rm, rGPR:$Rn),
2390 (t2QADD rGPR:$Rm, rGPR:$Rn)>;
2391 def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, rGPR:$Rn),
2392 (t2QSUB rGPR:$Rm, rGPR:$Rn)>;
2393 def : Thumb2DSPPat<(int_arm_qadd(int_arm_qadd rGPR:$Rm, rGPR:$Rm), rGPR:$Rn),
2394 (t2QDADD rGPR:$Rm, rGPR:$Rn)>;
2395 def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)),
2396 (t2QDSUB rGPR:$Rm, rGPR:$Rn)>;
2398 def : Thumb2DSPPat<(saddsat rGPR:$Rm, rGPR:$Rn),
2399 (t2QADD rGPR:$Rm, rGPR:$Rn)>;
2400 def : Thumb2DSPPat<(ssubsat rGPR:$Rm, rGPR:$Rn),
2401 (t2QSUB rGPR:$Rm, rGPR:$Rn)>;
2402 def : Thumb2DSPPat<(saddsat(saddsat rGPR:$Rm, rGPR:$Rm), rGPR:$Rn),
2403 (t2QDADD rGPR:$Rm, rGPR:$Rn)>;
2404 def : Thumb2DSPPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
2405 (t2QDSUB rGPR:$Rm, rGPR:$Rn)>;
2406 def : Thumb2DSPPat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),
2407 (t2QADD8 rGPR:$Rm, rGPR:$Rn)>;
2408 def : Thumb2DSPPat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),
2409 (t2QSUB8 rGPR:$Rm, rGPR:$Rn)>;
2410 def : Thumb2DSPPat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn),
2411 (t2QADD16 rGPR:$Rm, rGPR:$Rn)>;
2412 def : Thumb2DSPPat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn),
2413 (t2QSUB16 rGPR:$Rm, rGPR:$Rn)>;
2415 // Signed/Unsigned add/subtract
2417 def t2SASX : T2I_pam_intrinsics<0b010, 0b0000, "sasx", int_arm_sasx>;
2418 def t2SADD16 : T2I_pam_intrinsics<0b001, 0b0000, "sadd16", int_arm_sadd16>;
2419 def t2SADD8 : T2I_pam_intrinsics<0b000, 0b0000, "sadd8", int_arm_sadd8>;
2420 def t2SSAX : T2I_pam_intrinsics<0b110, 0b0000, "ssax", int_arm_ssax>;
2421 def t2SSUB16 : T2I_pam_intrinsics<0b101, 0b0000, "ssub16", int_arm_ssub16>;
2422 def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>;
2423 def t2UASX : T2I_pam_intrinsics<0b010, 0b0100, "uasx", int_arm_uasx>;
2424 def t2UADD16 : T2I_pam_intrinsics<0b001, 0b0100, "uadd16", int_arm_uadd16>;
2425 def t2UADD8 : T2I_pam_intrinsics<0b000, 0b0100, "uadd8", int_arm_uadd8>;
2426 def t2USAX : T2I_pam_intrinsics<0b110, 0b0100, "usax", int_arm_usax>;
2427 def t2USUB16 : T2I_pam_intrinsics<0b101, 0b0100, "usub16", int_arm_usub16>;
2428 def t2USUB8 : T2I_pam_intrinsics<0b100, 0b0100, "usub8", int_arm_usub8>;
2430 // Signed/Unsigned halving add/subtract
2432 def t2SHASX : T2I_pam_intrinsics<0b010, 0b0010, "shasx", int_arm_shasx>;
2433 def t2SHADD16 : T2I_pam_intrinsics<0b001, 0b0010, "shadd16", int_arm_shadd16>;
2434 def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>;
2435 def t2SHSAX : T2I_pam_intrinsics<0b110, 0b0010, "shsax", int_arm_shsax>;
2436 def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>;
2437 def t2SHSUB8 : T2I_pam_intrinsics<0b100, 0b0010, "shsub8", int_arm_shsub8>;
2438 def t2UHASX : T2I_pam_intrinsics<0b010, 0b0110, "uhasx", int_arm_uhasx>;
2439 def t2UHADD16 : T2I_pam_intrinsics<0b001, 0b0110, "uhadd16", int_arm_uhadd16>;
2440 def t2UHADD8 : T2I_pam_intrinsics<0b000, 0b0110, "uhadd8", int_arm_uhadd8>;
2441 def t2UHSAX : T2I_pam_intrinsics<0b110, 0b0110, "uhsax", int_arm_uhsax>;
2442 def t2UHSUB16 : T2I_pam_intrinsics<0b101, 0b0110, "uhsub16", int_arm_uhsub16>;
2443 def t2UHSUB8 : T2I_pam_intrinsics<0b100, 0b0110, "uhsub8", int_arm_uhsub8>;
2445 // Helper class for disassembly only
2446 // A6.3.16 & A6.3.17
2447 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2448 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2449 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2450 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2451 let Inst{31-27} = 0b11111;
2452 let Inst{26-24} = 0b011;
2453 let Inst{23} = long;
2454 let Inst{22-20} = op22_20;
2455 let Inst{7-4} = op7_4;
2458 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2459 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2460 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2461 let Inst{31-27} = 0b11111;
2462 let Inst{26-24} = 0b011;
2463 let Inst{23} = long;
2464 let Inst{22-20} = op22_20;
2465 let Inst{7-4} = op7_4;
2468 // Unsigned Sum of Absolute Differences [and Accumulate].
2469 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2470 (ins rGPR:$Rn, rGPR:$Rm),
2471 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm",
2472 [(set rGPR:$Rd, (int_arm_usad8 rGPR:$Rn, rGPR:$Rm))]>,
2473 Requires<[IsThumb2, HasDSP]> {
2474 let Inst{15-12} = 0b1111;
2476 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2477 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2478 "usada8", "\t$Rd, $Rn, $Rm, $Ra",
2479 [(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,
2480 Requires<[IsThumb2, HasDSP]>;
2482 // Signed/Unsigned saturate.
2483 let hasSideEffects = 1 in
2484 class T2SatI<dag iops, string opc, string asm>
2485 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> {
2491 let Inst{31-24} = 0b11110011;
2492 let Inst{21} = sh{5};
2494 let Inst{19-16} = Rn;
2496 let Inst{14-12} = sh{4-2};
2497 let Inst{11-8} = Rd;
2498 let Inst{7-6} = sh{1-0};
2500 let Inst{4-0} = sat_imm;
2503 def t2SSAT: T2SatI<(ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2504 "ssat", "\t$Rd, $sat_imm, $Rn$sh">,
2505 Requires<[IsThumb2]>, Sched<[WriteALU]> {
2506 let Inst{23-22} = 0b00;
2510 def t2SSAT16: T2SatI<(ins imm1_16:$sat_imm, rGPR:$Rn),
2511 "ssat16", "\t$Rd, $sat_imm, $Rn">,
2512 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
2513 let Inst{23-22} = 0b00;
2518 def t2USAT: T2SatI<(ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2519 "usat", "\t$Rd, $sat_imm, $Rn$sh">,
2520 Requires<[IsThumb2]>, Sched<[WriteALU]> {
2521 let Inst{23-22} = 0b10;
2524 def t2USAT16: T2SatI<(ins imm0_15:$sat_imm, rGPR:$Rn),
2525 "usat16", "\t$Rd, $sat_imm, $Rn">,
2526 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
2527 let Inst{23-22} = 0b10;
2532 def : T2Pat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
2533 (t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
2534 def : T2Pat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm),
2535 (t2USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
2536 def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos),
2537 (t2SSAT imm1_32:$pos, GPR:$a, 0)>;
2538 def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos),
2539 (t2USAT imm0_31:$pos, GPR:$a, 0)>;
2540 def : T2Pat<(int_arm_ssat16 GPR:$a, imm1_16:$pos),
2541 (t2SSAT16 imm1_16:$pos, GPR:$a)>;
2542 def : T2Pat<(int_arm_usat16 GPR:$a, imm0_15:$pos),
2543 (t2USAT16 imm0_15:$pos, GPR:$a)>;
2545 //===----------------------------------------------------------------------===//
2546 // Shift and rotate Instructions.
2549 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, shl>;
2550 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>;
2551 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>;
2552 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, rotr>;
2554 // LSL #0 is actually MOV, and has slightly different permitted registers to
2555 // LSL with non-zero shift
2556 def : t2InstAlias<"lsl${s}${p} $Rd, $Rm, #0",
2557 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
2558 def : t2InstAlias<"lsl${s}${p}.w $Rd, $Rm, #0",
2559 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
2561 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2562 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2563 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2565 let Uses = [CPSR] in {
2566 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2567 "rrx", "\t$Rd, $Rm",
2568 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2569 let Inst{31-27} = 0b11101;
2570 let Inst{26-25} = 0b01;
2571 let Inst{24-21} = 0b0010;
2572 let Inst{19-16} = 0b1111; // Rn
2574 let Unpredictable{15} = 0b1;
2575 let Inst{14-12} = 0b000;
2576 let Inst{7-4} = 0b0011;
2580 let isCodeGenOnly = 1, Defs = [CPSR] in {
2581 def t2MOVsrl_flag : T2TwoRegShiftImm<
2582 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2583 "lsrs", ".w\t$Rd, $Rm, #1",
2584 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2586 let Inst{31-27} = 0b11101;
2587 let Inst{26-25} = 0b01;
2588 let Inst{24-21} = 0b0010;
2589 let Inst{20} = 1; // The S bit.
2590 let Inst{19-16} = 0b1111; // Rn
2591 let Inst{5-4} = 0b01; // Shift type.
2592 // Shift amount = Inst{14-12:7-6} = 1.
2593 let Inst{14-12} = 0b000;
2594 let Inst{7-6} = 0b01;
2596 def t2MOVsra_flag : T2TwoRegShiftImm<
2597 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2598 "asrs", ".w\t$Rd, $Rm, #1",
2599 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2601 let Inst{31-27} = 0b11101;
2602 let Inst{26-25} = 0b01;
2603 let Inst{24-21} = 0b0010;
2604 let Inst{20} = 1; // The S bit.
2605 let Inst{19-16} = 0b1111; // Rn
2606 let Inst{5-4} = 0b10; // Shift type.
2607 // Shift amount = Inst{14-12:7-6} = 1.
2608 let Inst{14-12} = 0b000;
2609 let Inst{7-6} = 0b01;
2613 //===----------------------------------------------------------------------===//
2614 // Bitwise Instructions.
2617 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2618 IIC_iBITi, IIC_iBITr, IIC_iBITsi, and, 1>;
2619 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2620 IIC_iBITi, IIC_iBITr, IIC_iBITsi, or, 1>;
2621 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2622 IIC_iBITi, IIC_iBITr, IIC_iBITsi, xor, 1>;
2624 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2625 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2626 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2628 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2629 string opc, string asm, list<dag> pattern>
2630 : T2I<oops, iops, itin, opc, asm, pattern> {
2635 let Inst{11-8} = Rd;
2636 let Inst{4-0} = msb{4-0};
2637 let Inst{14-12} = lsb{4-2};
2638 let Inst{7-6} = lsb{1-0};
2641 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2642 string opc, string asm, list<dag> pattern>
2643 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2646 let Inst{19-16} = Rn;
2649 let Constraints = "$src = $Rd" in
2650 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2651 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2652 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> {
2653 let Inst{31-27} = 0b11110;
2654 let Inst{26} = 0; // should be 0.
2656 let Inst{24-20} = 0b10110;
2657 let Inst{19-16} = 0b1111; // Rn
2659 let Inst{5} = 0; // should be 0.
2662 let msb{4-0} = imm{9-5};
2663 let lsb{4-0} = imm{4-0};
2666 def t2SBFX: T2TwoRegBitFI<
2667 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2668 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
2669 let Inst{31-27} = 0b11110;
2671 let Inst{24-20} = 0b10100;
2675 def t2UBFX: T2TwoRegBitFI<
2676 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2677 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
2678 let Inst{31-27} = 0b11110;
2680 let Inst{24-20} = 0b11100;
2684 // A8.8.247 UDF - Undefined (Encoding T2)
2685 def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",
2686 [(int_arm_undefined imm0_65535:$imm16)]> {
2688 let Inst{31-29} = 0b111;
2689 let Inst{28-27} = 0b10;
2690 let Inst{26-20} = 0b1111111;
2691 let Inst{19-16} = imm16{15-12};
2693 let Inst{14-12} = 0b010;
2694 let Inst{11-0} = imm16{11-0};
2697 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2698 let Constraints = "$src = $Rd" in {
2699 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2700 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2701 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2702 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2703 bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> {
2704 let Inst{31-27} = 0b11110;
2705 let Inst{26} = 0; // should be 0.
2707 let Inst{24-20} = 0b10110;
2709 let Inst{5} = 0; // should be 0.
2712 let msb{4-0} = imm{9-5};
2713 let lsb{4-0} = imm{4-0};
2717 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2718 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2719 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2721 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2722 /// unary operation that produces a value. These are predicable and can be
2723 /// changed to modify CPSR.
2724 multiclass T2I_un_irs<bits<4> opcod, string opc,
2725 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2727 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2729 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2731 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2732 let isAsCheapAsAMove = Cheap;
2733 let isReMaterializable = ReMat;
2734 let isMoveImm = MoveImm;
2735 let Inst{31-27} = 0b11110;
2737 let Inst{24-21} = opcod;
2738 let Inst{19-16} = 0b1111; // Rn
2742 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2743 opc, ".w\t$Rd, $Rm",
2744 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2745 let Inst{31-27} = 0b11101;
2746 let Inst{26-25} = 0b01;
2747 let Inst{24-21} = opcod;
2748 let Inst{19-16} = 0b1111; // Rn
2749 let Inst{14-12} = 0b000; // imm3
2750 let Inst{7-6} = 0b00; // imm2
2751 let Inst{5-4} = 0b00; // type
2754 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2755 opc, ".w\t$Rd, $ShiftedRm",
2756 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2758 let Inst{31-27} = 0b11101;
2759 let Inst{26-25} = 0b01;
2760 let Inst{24-21} = opcod;
2761 let Inst{19-16} = 0b1111; // Rn
2765 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2766 let AddedComplexity = 1 in
2767 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2768 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2771 let AddedComplexity = 1 in
2772 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2773 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2775 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2776 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2777 return !SDValue(N,0)->getValueType(0).isVector() &&
2778 CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2781 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2782 // will match the extended, not the original bitWidth for $src.
2783 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2784 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2787 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2788 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2789 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2790 Requires<[IsThumb2]>;
2792 def : T2Pat<(t2_so_imm_not:$src),
2793 (t2MVNi t2_so_imm_not:$src)>;
2795 // There are shorter Thumb encodings for ADD than ORR, so to increase
2796 // Thumb2SizeReduction's chances later on we select a t2ADD for an or where
2798 def : T2Pat<(or AddLikeOrOp:$Rn, t2_so_imm:$imm),
2799 (t2ADDri $Rn, t2_so_imm:$imm)>;
2801 def : T2Pat<(or AddLikeOrOp:$Rn, imm0_4095:$Rm),
2802 (t2ADDri12 $Rn, imm0_4095:$Rm)>;
2804 def : T2Pat<(or AddLikeOrOp:$Rn, non_imm32:$Rm),
2805 (t2ADDrr $Rn, $Rm)>;
2807 //===----------------------------------------------------------------------===//
2808 // Multiply Instructions.
2810 let isCommutable = 1 in
2811 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2812 "mul", "\t$Rd, $Rn, $Rm",
2813 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]>,
2814 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
2815 let Inst{31-27} = 0b11111;
2816 let Inst{26-23} = 0b0110;
2817 let Inst{22-20} = 0b000;
2818 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2819 let Inst{7-4} = 0b0000; // Multiply
2822 class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern>
2823 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2824 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2825 Requires<[IsThumb2, UseMulOps]>,
2826 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
2827 let Inst{31-27} = 0b11111;
2828 let Inst{26-23} = 0b0110;
2829 let Inst{22-20} = 0b000;
2830 let Inst{7-4} = op7_4;
2833 def t2MLA : T2FourRegMLA<0b0000, "mla",
2834 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
2836 def t2MLS: T2FourRegMLA<0b0001, "mls",
2837 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
2840 // Extra precision multiplies with low / high results
2841 let hasSideEffects = 0 in {
2842 let isCommutable = 1 in {
2843 def t2SMULL : T2MulLong<0b000, 0b0000, "smull",
2844 [(set rGPR:$RdLo, rGPR:$RdHi,
2845 (smullohi rGPR:$Rn, rGPR:$Rm))]>;
2846 def t2UMULL : T2MulLong<0b010, 0b0000, "umull",
2847 [(set rGPR:$RdLo, rGPR:$RdHi,
2848 (umullohi rGPR:$Rn, rGPR:$Rm))]>;
2851 // Multiply + accumulate
2852 def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;
2853 def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;
2854 def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;
2857 // Rounding variants of the below included for disassembly only
2859 // Most significant word multiply
2860 class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern>
2861 : T2ThreeReg<(outs rGPR:$Rd),
2862 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2863 opc, "\t$Rd, $Rn, $Rm", pattern>,
2864 Requires<[IsThumb2, HasDSP]>,
2865 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
2866 let Inst{31-27} = 0b11111;
2867 let Inst{26-23} = 0b0110;
2868 let Inst{22-20} = 0b101;
2869 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2870 let Inst{7-4} = op7_4;
2872 def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
2875 T2SMMUL<0b0001, "smmulr",
2876 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, (i32 0)))]>;
2878 class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
2880 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2881 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2882 Requires<[IsThumb2, HasDSP, UseMulOps]>,
2883 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
2884 let Inst{31-27} = 0b11111;
2885 let Inst{26-23} = 0b0110;
2886 let Inst{22-20} = op22_20;
2887 let Inst{7-4} = op7_4;
2890 def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
2891 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
2892 def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar",
2893 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>;
2894 def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>;
2895 def t2SMMLSR: T2FourRegSMMLA<0b110, 0b0001, "smmlsr",
2896 [(set rGPR:$Rd, (ARMsmmlsr rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>;
2898 class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
2900 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
2901 "\t$Rd, $Rn, $Rm", pattern>,
2902 Requires<[IsThumb2, HasDSP]>,
2903 Sched<[WriteMUL16, ReadMUL, ReadMUL]> {
2904 let Inst{31-27} = 0b11111;
2905 let Inst{26-23} = 0b0110;
2906 let Inst{22-20} = op22_20;
2907 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2908 let Inst{7-6} = 0b00;
2909 let Inst{5-4} = op5_4;
2912 def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
2913 [(set rGPR:$Rd, (bb_mul rGPR:$Rn, rGPR:$Rm))]>;
2914 def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
2915 [(set rGPR:$Rd, (bt_mul rGPR:$Rn, rGPR:$Rm))]>;
2916 def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
2917 [(set rGPR:$Rd, (tb_mul rGPR:$Rn, rGPR:$Rm))]>;
2918 def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
2919 [(set rGPR:$Rd, (tt_mul rGPR:$Rn, rGPR:$Rm))]>;
2920 def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb",
2921 [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>;
2922 def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt",
2923 [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>;
2925 def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_bottom_16 rGPR:$Rm)),
2926 (t2SMULBB rGPR:$Rn, rGPR:$Rm)>;
2927 def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_top_16 rGPR:$Rm)),
2928 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>;
2929 def : Thumb2DSPPat<(mul (sext_top_16 rGPR:$Rn), sext_16_node:$Rm),
2930 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>;
2932 def : Thumb2DSPPat<(int_arm_smulbb rGPR:$Rn, rGPR:$Rm),
2933 (t2SMULBB rGPR:$Rn, rGPR:$Rm)>;
2934 def : Thumb2DSPPat<(int_arm_smulbt rGPR:$Rn, rGPR:$Rm),
2935 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>;
2936 def : Thumb2DSPPat<(int_arm_smultb rGPR:$Rn, rGPR:$Rm),
2937 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>;
2938 def : Thumb2DSPPat<(int_arm_smultt rGPR:$Rn, rGPR:$Rm),
2939 (t2SMULTT rGPR:$Rn, rGPR:$Rm)>;
2940 def : Thumb2DSPPat<(int_arm_smulwb rGPR:$Rn, rGPR:$Rm),
2941 (t2SMULWB rGPR:$Rn, rGPR:$Rm)>;
2942 def : Thumb2DSPPat<(int_arm_smulwt rGPR:$Rn, rGPR:$Rm),
2943 (t2SMULWT rGPR:$Rn, rGPR:$Rm)>;
2945 class T2FourRegSMLA<bits<3> op22_20, bits<2> op5_4, string opc,
2947 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
2948 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2949 Requires<[IsThumb2, HasDSP, UseMulOps]>,
2950 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]> {
2951 let Inst{31-27} = 0b11111;
2952 let Inst{26-23} = 0b0110;
2953 let Inst{22-20} = op22_20;
2954 let Inst{7-6} = 0b00;
2955 let Inst{5-4} = op5_4;
2958 def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb",
2959 [(set rGPR:$Rd, (add rGPR:$Ra, (bb_mul rGPR:$Rn, rGPR:$Rm)))]>;
2960 def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt",
2961 [(set rGPR:$Rd, (add rGPR:$Ra, (bt_mul rGPR:$Rn, rGPR:$Rm)))]>;
2962 def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb",
2963 [(set rGPR:$Rd, (add rGPR:$Ra, (tb_mul rGPR:$Rn, rGPR:$Rm)))]>;
2964 def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt",
2965 [(set rGPR:$Rd, (add rGPR:$Ra, (tt_mul rGPR:$Rn, rGPR:$Rm)))]>;
2966 def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
2967 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>;
2968 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
2969 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>;
2971 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)),
2972 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2973 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn,
2974 (sext_bottom_16 rGPR:$Rm))),
2975 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2976 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn,
2977 (sext_top_16 rGPR:$Rm))),
2978 (t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2979 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul (sext_top_16 rGPR:$Rn),
2981 (t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2983 def : Thumb2DSPPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc),
2984 (t2SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2985 def : Thumb2DSPPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc),
2986 (t2SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2987 def : Thumb2DSPPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc),
2988 (t2SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2989 def : Thumb2DSPPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc),
2990 (t2SMLATT GPR:$a, GPR:$b, GPR:$acc)>;
2991 def : Thumb2DSPPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc),
2992 (t2SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2993 def : Thumb2DSPPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc),
2994 (t2SMLAWT GPR:$a, GPR:$b, GPR:$acc)>;
2996 // Halfword multiple accumulate long: SMLAL<x><y>
2997 def t2SMLALBB : T2MlaLong<0b100, 0b1000, "smlalbb">,
2998 Requires<[IsThumb2, HasDSP]>;
2999 def t2SMLALBT : T2MlaLong<0b100, 0b1001, "smlalbt">,
3000 Requires<[IsThumb2, HasDSP]>;
3001 def t2SMLALTB : T2MlaLong<0b100, 0b1010, "smlaltb">,
3002 Requires<[IsThumb2, HasDSP]>;
3003 def t2SMLALTT : T2MlaLong<0b100, 0b1011, "smlaltt">,
3004 Requires<[IsThumb2, HasDSP]>;
3006 def : Thumb2DSPPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
3007 (t2SMLALBB $Rn, $Rm, $RLo, $RHi)>;
3008 def : Thumb2DSPPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
3009 (t2SMLALBT $Rn, $Rm, $RLo, $RHi)>;
3010 def : Thumb2DSPPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
3011 (t2SMLALTB $Rn, $Rm, $RLo, $RHi)>;
3012 def : Thumb2DSPPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
3013 (t2SMLALTT $Rn, $Rm, $RLo, $RHi)>;
3015 class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc,
3016 Intrinsic intrinsic>
3017 : T2ThreeReg_mac<0, op22_20, op7_4,
3019 (ins rGPR:$Rn, rGPR:$Rm),
3020 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm",
3021 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))]>,
3022 Requires<[IsThumb2, HasDSP]>,
3023 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
3024 let Inst{15-12} = 0b1111;
3027 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
3028 def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad", int_arm_smuad>;
3029 def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx", int_arm_smuadx>;
3030 def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd", int_arm_smusd>;
3031 def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx", int_arm_smusdx>;
3033 class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc,
3034 Intrinsic intrinsic>
3035 : T2FourReg_mac<0, op22_20, op7_4,
3037 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
3038 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra",
3039 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,
3040 Requires<[IsThumb2, HasDSP]>;
3042 def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad", int_arm_smlad>;
3043 def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx", int_arm_smladx>;
3044 def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd", int_arm_smlsd>;
3045 def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx", int_arm_smlsdx>;
3047 class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc>
3048 : T2FourReg_mac<1, op22_20, op7_4,
3049 (outs rGPR:$Ra, rGPR:$Rd),
3050 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
3051 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
3052 RegConstraint<"$Ra = $RLo, $Rd = $RHi">,
3053 Requires<[IsThumb2, HasDSP]>,
3054 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
3056 def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
3057 def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
3058 def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
3059 def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
3061 def : Thumb2DSPPat<(ARMSmlald rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
3062 (t2SMLALD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;
3063 def : Thumb2DSPPat<(ARMSmlaldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
3064 (t2SMLALDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;
3065 def : Thumb2DSPPat<(ARMSmlsld rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
3066 (t2SMLSLD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;
3067 def : Thumb2DSPPat<(ARMSmlsldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
3068 (t2SMLSLDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;
3070 //===----------------------------------------------------------------------===//
3071 // Division Instructions.
3072 // Signed and unsigned division on v7-M
3074 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
3075 "sdiv", "\t$Rd, $Rn, $Rm",
3076 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
3077 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>,
3079 let Inst{31-27} = 0b11111;
3080 let Inst{26-21} = 0b011100;
3082 let Inst{15-12} = 0b1111;
3083 let Inst{7-4} = 0b1111;
3086 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
3087 "udiv", "\t$Rd, $Rn, $Rm",
3088 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
3089 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>,
3091 let Inst{31-27} = 0b11111;
3092 let Inst{26-21} = 0b011101;
3094 let Inst{15-12} = 0b1111;
3095 let Inst{7-4} = 0b1111;
3098 //===----------------------------------------------------------------------===//
3099 // Misc. Arithmetic Instructions.
3102 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
3103 InstrItinClass itin, string opc, string asm, list<dag> pattern>
3104 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
3105 let Inst{31-27} = 0b11111;
3106 let Inst{26-22} = 0b01010;
3107 let Inst{21-20} = op1;
3108 let Inst{15-12} = 0b1111;
3109 let Inst{7-6} = 0b10;
3110 let Inst{5-4} = op2;
3114 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3115 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
3118 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3119 "rbit", "\t$Rd, $Rm",
3120 [(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>,
3123 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3124 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
3127 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3128 "rev16", ".w\t$Rd, $Rm",
3129 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
3132 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3133 "revsh", ".w\t$Rd, $Rm",
3134 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
3137 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
3138 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
3139 (t2REVSH rGPR:$Rm)>;
3141 def t2PKHBT : T2ThreeReg<
3142 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
3143 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3144 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
3145 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
3147 Requires<[HasDSP, IsThumb2]>,
3148 Sched<[WriteALUsi, ReadALU]> {
3149 let Inst{31-27} = 0b11101;
3150 let Inst{26-25} = 0b01;
3151 let Inst{24-20} = 0b01100;
3152 let Inst{5} = 0; // BT form
3156 let Inst{14-12} = sh{4-2};
3157 let Inst{7-6} = sh{1-0};
3160 // Alternate cases for PKHBT where identities eliminate some nodes.
3161 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
3162 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
3163 Requires<[HasDSP, IsThumb2]>;
3164 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
3165 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
3166 Requires<[HasDSP, IsThumb2]>;
3168 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3169 // will match the pattern below.
3170 def t2PKHTB : T2ThreeReg<
3171 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
3172 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3173 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
3174 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
3176 Requires<[HasDSP, IsThumb2]>,
3177 Sched<[WriteALUsi, ReadALU]> {
3178 let Inst{31-27} = 0b11101;
3179 let Inst{26-25} = 0b01;
3180 let Inst{24-20} = 0b01100;
3181 let Inst{5} = 1; // TB form
3185 let Inst{14-12} = sh{4-2};
3186 let Inst{7-6} = sh{1-0};
3189 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3190 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3191 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
3192 // pkhtb src1, src2, asr (17..31).
3193 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
3194 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,
3195 Requires<[HasDSP, IsThumb2]>;
3196 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
3197 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
3198 Requires<[HasDSP, IsThumb2]>;
3199 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
3200 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
3201 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
3202 Requires<[HasDSP, IsThumb2]>;
3204 //===----------------------------------------------------------------------===//
3205 // CRC32 Instructions
3208 // + CRC32{B,H,W} 0x04C11DB7
3209 // + CRC32C{B,H,W} 0x1EDC6F41
3212 class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
3213 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
3214 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
3215 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
3216 Requires<[IsThumb2, HasV8, HasCRC]> {
3217 let Inst{31-27} = 0b11111;
3218 let Inst{26-21} = 0b010110;
3220 let Inst{15-12} = 0b1111;
3221 let Inst{7-6} = 0b10;
3225 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
3226 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
3227 def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;
3228 def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;
3229 def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>;
3230 def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>;
3232 //===----------------------------------------------------------------------===//
3233 // Comparison Instructions...
3235 defm t2CMP : T2I_cmp_irs<0b1101, "cmp", GPRnopc,
3236 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, ARMcmp>;
3238 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
3239 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
3240 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
3241 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
3242 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
3243 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
3245 let isCompare = 1, Defs = [CPSR] in {
3247 def t2CMNri : T2OneRegCmpImm<
3248 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
3249 "cmn", ".w\t$Rn, $imm",
3250 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
3251 Sched<[WriteCMP, ReadALU]> {
3252 let Inst{31-27} = 0b11110;
3254 let Inst{24-21} = 0b1000;
3255 let Inst{20} = 1; // The S bit.
3257 let Inst{11-8} = 0b1111; // Rd
3260 def t2CMNzrr : T2TwoRegCmp<
3261 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
3262 "cmn", ".w\t$Rn, $Rm",
3263 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3264 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
3265 let Inst{31-27} = 0b11101;
3266 let Inst{26-25} = 0b01;
3267 let Inst{24-21} = 0b1000;
3268 let Inst{20} = 1; // The S bit.
3269 let Inst{14-12} = 0b000; // imm3
3270 let Inst{11-8} = 0b1111; // Rd
3271 let Inst{7-6} = 0b00; // imm2
3272 let Inst{5-4} = 0b00; // type
3275 def t2CMNzrs : T2OneRegCmpShiftedReg<
3276 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
3277 "cmn", ".w\t$Rn, $ShiftedRm",
3278 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3279 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
3280 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
3281 let Inst{31-27} = 0b11101;
3282 let Inst{26-25} = 0b01;
3283 let Inst{24-21} = 0b1000;
3284 let Inst{20} = 1; // The S bit.
3285 let Inst{11-8} = 0b1111; // Rd
3289 // Assembler aliases w/o the ".w" suffix.
3290 // No alias here for 'rr' version as not all instantiations of this multiclass
3291 // want one (CMP in particular, does not).
3292 def : t2InstAlias<"cmn${p} $Rn, $imm",
3293 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
3294 def : t2InstAlias<"cmn${p} $Rn, $shift",
3295 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
3297 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
3298 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
3300 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
3301 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
3303 defm t2TST : T2I_cmp_irs<0b0000, "tst", rGPR,
3304 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3305 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
3306 defm t2TEQ : T2I_cmp_irs<0b0100, "teq", rGPR,
3307 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3308 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
3310 // Conditional moves
3311 let hasSideEffects = 0 in {
3313 let isCommutable = 1, isSelect = 1 in
3314 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3315 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p),
3317 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
3319 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3321 let isMoveImm = 1 in
3323 : t2PseudoInst<(outs rGPR:$Rd),
3324 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3326 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
3328 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3330 let isCodeGenOnly = 1 in {
3331 let isMoveImm = 1 in
3333 : t2PseudoInst<(outs rGPR:$Rd),
3334 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
3336 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
3338 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3340 let isMoveImm = 1 in
3342 : t2PseudoInst<(outs rGPR:$Rd),
3343 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3346 (ARMcmov rGPR:$false, t2_so_imm_not:$imm,
3348 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3350 class MOVCCShPseudo<SDPatternOperator opnode, Operand ty>
3351 : t2PseudoInst<(outs rGPR:$Rd),
3352 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p),
3354 [(set rGPR:$Rd, (ARMcmov rGPR:$false,
3355 (opnode rGPR:$Rm, (i32 ty:$imm)),
3357 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3359 def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>;
3360 def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>;
3361 def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>;
3362 def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>;
3364 let isMoveImm = 1 in
3366 : t2PseudoInst<(outs rGPR:$dst),
3367 (ins rGPR:$false, i32imm:$src, cmovpred:$p),
3369 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src,
3371 RegConstraint<"$false = $dst">;
3372 } // isCodeGenOnly = 1
3376 //===----------------------------------------------------------------------===//
3377 // Atomic operations intrinsics
3380 // memory barriers protect the atomic sequences
3381 let hasSideEffects = 1 in {
3382 def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3383 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
3384 Requires<[IsThumb, HasDB]> {
3386 let Inst{31-4} = 0xf3bf8f5;
3387 let Inst{3-0} = opt;
3390 def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3391 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
3392 Requires<[IsThumb, HasDB]> {
3394 let Inst{31-4} = 0xf3bf8f4;
3395 let Inst{3-0} = opt;
3398 def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
3399 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
3400 Requires<[IsThumb, HasDB]> {
3402 let Inst{31-4} = 0xf3bf8f6;
3403 let Inst{3-0} = opt;
3406 let hasNoSchedulingInfo = 1 in
3407 def t2TSB : T2I<(outs), (ins tsb_opt:$opt), NoItinerary,
3408 "tsb", "\t$opt", []>, Requires<[IsThumb, HasV8_4a]> {
3409 let Inst{31-0} = 0xf3af8012;
3413 // Armv8.5-A speculation barrier
3414 def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>,
3415 Requires<[IsThumb2, HasSB]>, Sched<[]> {
3416 let Inst{31-0} = 0xf3bf8f70;
3417 let Unpredictable = 0x000f2f0f;
3418 let hasSideEffects = 1;
3421 class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3422 InstrItinClass itin, string opc, string asm, string cstr,
3423 list<dag> pattern, bits<4> rt2 = 0b1111>
3424 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3425 let Inst{31-27} = 0b11101;
3426 let Inst{26-20} = 0b0001101;
3427 let Inst{11-8} = rt2;
3428 let Inst{7-4} = opcod;
3429 let Inst{3-0} = 0b1111;
3433 let Inst{19-16} = addr;
3434 let Inst{15-12} = Rt;
3436 class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3437 InstrItinClass itin, string opc, string asm, string cstr,
3438 list<dag> pattern, bits<4> rt2 = 0b1111>
3439 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3440 let Inst{31-27} = 0b11101;
3441 let Inst{26-20} = 0b0001100;
3442 let Inst{11-8} = rt2;
3443 let Inst{7-4} = opcod;
3449 let Inst{19-16} = addr;
3450 let Inst{15-12} = Rt;
3453 let mayLoad = 1 in {
3454 def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3455 AddrModeNone, 4, NoItinerary,
3456 "ldrexb", "\t$Rt, $addr", "",
3457 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>,
3458 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]>;
3459 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3460 AddrModeNone, 4, NoItinerary,
3461 "ldrexh", "\t$Rt, $addr", "",
3462 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>,
3463 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]>;
3464 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3465 AddrModeT2_ldrex, 4, NoItinerary,
3466 "ldrex", "\t$Rt, $addr", "",
3467 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]>,
3468 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]> {
3471 let Inst{31-27} = 0b11101;
3472 let Inst{26-20} = 0b0000101;
3473 let Inst{19-16} = addr{11-8};
3474 let Inst{15-12} = Rt;
3475 let Inst{11-8} = 0b1111;
3476 let Inst{7-0} = addr{7-0};
3478 let hasExtraDefRegAllocReq = 1 in
3479 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3480 (ins addr_offset_none:$addr),
3481 AddrModeNone, 4, NoItinerary,
3482 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3484 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteLd]> {
3486 let Inst{11-8} = Rt2;
3488 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3489 AddrModeNone, 4, NoItinerary,
3490 "ldaexb", "\t$Rt, $addr", "",
3491 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,
3492 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]>;
3493 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3494 AddrModeNone, 4, NoItinerary,
3495 "ldaexh", "\t$Rt, $addr", "",
3496 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>,
3497 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]>;
3498 def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),
3499 AddrModeNone, 4, NoItinerary,
3500 "ldaex", "\t$Rt, $addr", "",
3501 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>,
3502 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]> {
3505 let Inst{31-27} = 0b11101;
3506 let Inst{26-20} = 0b0001101;
3507 let Inst{19-16} = addr;
3508 let Inst{15-12} = Rt;
3509 let Inst{11-8} = 0b1111;
3510 let Inst{7-0} = 0b11101111;
3512 let hasExtraDefRegAllocReq = 1 in
3513 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3514 (ins addr_offset_none:$addr),
3515 AddrModeNone, 4, NoItinerary,
3516 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3517 [], {?, ?, ?, ?}>, Requires<[IsThumb,
3518 HasAcquireRelease, HasV7Clrex, IsNotMClass]>, Sched<[WriteLd]> {
3520 let Inst{11-8} = Rt2;
3526 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3527 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3528 (ins rGPR:$Rt, addr_offset_none:$addr),
3529 AddrModeNone, 4, NoItinerary,
3530 "strexb", "\t$Rd, $Rt, $addr", "",
3532 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3533 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]>;
3534 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3535 (ins rGPR:$Rt, addr_offset_none:$addr),
3536 AddrModeNone, 4, NoItinerary,
3537 "strexh", "\t$Rd, $Rt, $addr", "",
3539 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3540 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]>;
3542 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3543 t2addrmode_imm0_1020s4:$addr),
3544 AddrModeT2_ldrex, 4, NoItinerary,
3545 "strex", "\t$Rd, $Rt, $addr", "",
3547 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]>,
3548 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]> {
3552 let Inst{31-27} = 0b11101;
3553 let Inst{26-20} = 0b0000100;
3554 let Inst{19-16} = addr{11-8};
3555 let Inst{15-12} = Rt;
3556 let Inst{11-8} = Rd;
3557 let Inst{7-0} = addr{7-0};
3559 let hasExtraSrcRegAllocReq = 1 in
3560 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3561 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3562 AddrModeNone, 4, NoItinerary,
3563 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3565 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteST]> {
3567 let Inst{11-8} = Rt2;
3569 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3570 (ins rGPR:$Rt, addr_offset_none:$addr),
3571 AddrModeNone, 4, NoItinerary,
3572 "stlexb", "\t$Rd, $Rt, $addr", "",
3574 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3575 Requires<[IsThumb, HasAcquireRelease,
3576 HasV7Clrex]>, Sched<[WriteST]>;
3578 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3579 (ins rGPR:$Rt, addr_offset_none:$addr),
3580 AddrModeNone, 4, NoItinerary,
3581 "stlexh", "\t$Rd, $Rt, $addr", "",
3583 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3584 Requires<[IsThumb, HasAcquireRelease,
3585 HasV7Clrex]>, Sched<[WriteST]>;
3587 def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3588 addr_offset_none:$addr),
3589 AddrModeNone, 4, NoItinerary,
3590 "stlex", "\t$Rd, $Rt, $addr", "",
3592 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>,
3593 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>,
3598 let Inst{31-27} = 0b11101;
3599 let Inst{26-20} = 0b0001100;
3600 let Inst{19-16} = addr;
3601 let Inst{15-12} = Rt;
3602 let Inst{11-4} = 0b11111110;
3605 let hasExtraSrcRegAllocReq = 1 in
3606 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3607 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3608 AddrModeNone, 4, NoItinerary,
3609 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3610 {?, ?, ?, ?}>, Requires<[IsThumb, HasAcquireRelease,
3611 HasV7Clrex, IsNotMClass]>, Sched<[WriteST]> {
3613 let Inst{11-8} = Rt2;
3617 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
3618 Requires<[IsThumb, HasV7Clrex]> {
3619 let Inst{31-16} = 0xf3bf;
3620 let Inst{15-14} = 0b10;
3623 let Inst{11-8} = 0b1111;
3624 let Inst{7-4} = 0b0010;
3625 let Inst{3-0} = 0b1111;
3628 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
3629 (t2LDREXB addr_offset_none:$addr)>,
3630 Requires<[IsThumb, HasV8MBaseline]>;
3631 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
3632 (t2LDREXH addr_offset_none:$addr)>,
3633 Requires<[IsThumb, HasV8MBaseline]>;
3634 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3635 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>,
3636 Requires<[IsThumb, HasV8MBaseline]>;
3637 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3638 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>,
3639 Requires<[IsThumb, HasV8MBaseline]>;
3641 def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff),
3642 (t2LDAEXB addr_offset_none:$addr)>,
3643 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3644 def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),
3645 (t2LDAEXH addr_offset_none:$addr)>,
3646 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3647 def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3648 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>,
3649 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3650 def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3651 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>,
3652 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3654 //===----------------------------------------------------------------------===//
3655 // SJLJ Exception handling intrinsics
3656 // eh_sjlj_setjmp() is an instruction sequence to store the return
3657 // address and save #0 in R0 for the non-longjmp case.
3658 // Since by its nature we may be coming from some other function to get
3659 // here, and we're using the stack frame for the containing function to
3660 // save/restore registers, we can't keep anything live in regs across
3661 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3662 // when we get here from a longjmp(). We force everything out of registers
3663 // except for our own input by listing the relevant registers in Defs. By
3664 // doing so, we also cause the prologue/epilogue code to actively preserve
3665 // all of the callee-saved resgisters, which is exactly what we want.
3666 // $val is a scratch register for our use.
3668 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3669 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3670 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3671 usesCustomInserter = 1 in {
3672 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3673 AddrModeNone, 0, NoItinerary, "", "",
3674 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3675 Requires<[IsThumb2, HasVFP2]>;
3679 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3680 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3681 usesCustomInserter = 1 in {
3682 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3683 AddrModeNone, 0, NoItinerary, "", "",
3684 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3685 Requires<[IsThumb2, NoVFP]>;
3689 //===----------------------------------------------------------------------===//
3690 // Control-Flow Instructions
3693 // FIXME: remove when we have a way to marking a MI with these properties.
3694 // FIXME: Should pc be an implicit operand like PICADD, etc?
3695 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3696 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3697 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3698 reglist:$regs, variable_ops),
3699 4, IIC_iLoad_mBr, [],
3700 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3701 RegConstraint<"$Rn = $wb">;
3703 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3704 let isPredicable = 1 in
3705 def t2B : T2I<(outs), (ins thumb_br_target:$target), IIC_Br,
3707 [(br bb:$target)]>, Sched<[WriteBr]>,
3708 Requires<[IsThumb, HasV8MBaseline]> {
3709 let Inst{31-27} = 0b11110;
3710 let Inst{15-14} = 0b10;
3714 let Inst{26} = target{23};
3715 let Inst{13} = target{22};
3716 let Inst{11} = target{21};
3717 let Inst{25-16} = target{20-11};
3718 let Inst{10-0} = target{10-0};
3719 let DecoderMethod = "DecodeT2BInstruction";
3720 let AsmMatchConverter = "cvtThumbBranches";
3723 let Size = 4, isNotDuplicable = 1, isBranch = 1, isTerminator = 1,
3724 isBarrier = 1, isIndirectBranch = 1 in {
3726 // available in both v8-M.Baseline and Thumb2 targets
3727 def t2BR_JT : t2basePseudoInst<(outs),
3728 (ins GPR:$target, GPR:$index, i32imm:$jt),
3730 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)]>,
3733 // FIXME: Add a case that can be predicated.
3734 def t2TBB_JT : t2PseudoInst<(outs),
3735 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3738 def t2TBH_JT : t2PseudoInst<(outs),
3739 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3742 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3743 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3746 let Inst{31-20} = 0b111010001101;
3747 let Inst{19-16} = Rn;
3748 let Inst{15-5} = 0b11110000000;
3749 let Inst{4} = 0; // B form
3752 let DecoderMethod = "DecodeThumbTableBranch";
3755 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3756 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3759 let Inst{31-20} = 0b111010001101;
3760 let Inst{19-16} = Rn;
3761 let Inst{15-5} = 0b11110000000;
3762 let Inst{4} = 1; // H form
3765 let DecoderMethod = "DecodeThumbTableBranch";
3767 } // isNotDuplicable, isIndirectBranch
3769 } // isBranch, isTerminator, isBarrier
3771 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3772 // a two-value operand where a dag node expects ", "two operands. :(
3773 let isBranch = 1, isTerminator = 1 in
3774 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3776 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3777 let Inst{31-27} = 0b11110;
3778 let Inst{15-14} = 0b10;
3782 let Inst{25-22} = p;
3785 let Inst{26} = target{20};
3786 let Inst{11} = target{19};
3787 let Inst{13} = target{18};
3788 let Inst{21-16} = target{17-12};
3789 let Inst{10-0} = target{11-1};
3791 let DecoderMethod = "DecodeThumb2BCCInstruction";
3792 let AsmMatchConverter = "cvtThumbBranches";
3795 // Tail calls. The MachO version of thumb tail calls uses a t2 branch, so
3797 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3800 def tTAILJMPd: tPseudoExpand<(outs),
3801 (ins thumb_br_target:$dst, pred:$p),
3803 (t2B thumb_br_target:$dst, pred:$p)>,
3804 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>;
3808 let Defs = [ITSTATE] in
3809 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3810 AddrModeNone, 2, IIC_iALUx,
3811 "it$mask\t$cc", "", []>,
3812 ComplexDeprecationPredicate<"IT"> {
3813 // 16-bit instruction.
3814 let Inst{31-16} = 0x0000;
3815 let Inst{15-8} = 0b10111111;
3820 let Inst{3-0} = mask;
3822 let DecoderMethod = "DecodeIT";
3825 // Branch and Exchange Jazelle -- for disassembly only
3827 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
3828 def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>,
3829 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
3831 let Inst{31-27} = 0b11110;
3833 let Inst{25-20} = 0b111100;
3834 let Inst{19-16} = func;
3835 let Inst{15-0} = 0b1000111100000000;
3838 // Compare and branch on zero / non-zero
3839 let isBranch = 1, isTerminator = 1 in {
3840 def tCBZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
3841 "cbz\t$Rn, $target", []>,
3842 T1Misc<{0,0,?,1,?,?,?}>,
3843 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
3847 let Inst{9} = target{5};
3848 let Inst{7-3} = target{4-0};
3852 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
3853 "cbnz\t$Rn, $target", []>,
3854 T1Misc<{1,0,?,1,?,?,?}>,
3855 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
3859 let Inst{9} = target{5};
3860 let Inst{7-3} = target{4-0};
3866 // Change Processor State is a system instruction.
3867 // FIXME: Since the asm parser has currently no clean way to handle optional
3868 // operands, create 3 versions of the same instruction. Once there's a clean
3869 // framework to represent optional operands, change this behavior.
3870 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3871 !strconcat("cps", asm_op), []>,
3872 Requires<[IsThumb2, IsNotMClass]> {
3878 let Inst{31-11} = 0b111100111010111110000;
3879 let Inst{10-9} = imod;
3881 let Inst{7-5} = iflags;
3882 let Inst{4-0} = mode;
3883 let DecoderMethod = "DecodeT2CPSInstruction";
3887 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3888 "$imod\t$iflags, $mode">;
3889 let mode = 0, M = 0 in
3890 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3891 "$imod.w\t$iflags">;
3892 let imod = 0, iflags = 0, M = 1 in
3893 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3895 def : t2InstAlias<"cps$imod.w $iflags, $mode",
3896 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;
3897 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
3899 // A6.3.4 Branches and miscellaneous control
3900 // Table A6-14 Change Processor State, and hint instructions
3901 def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
3902 [(int_arm_hint imm0_239:$imm)]> {
3904 let Inst{31-3} = 0b11110011101011111000000000000;
3905 let Inst{7-0} = imm;
3908 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;
3909 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
3910 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;
3911 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;
3912 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;
3913 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
3914 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
3915 let Predicates = [IsThumb2, HasV8];
3917 def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> {
3918 let Predicates = [IsThumb2, HasRAS];
3920 def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
3921 let Predicates = [IsThumb2, HasRAS];
3923 def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>;
3924 def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>;
3926 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
3927 [(int_arm_dbg imm0_15:$opt)]> {
3929 let Inst{31-20} = 0b111100111010;
3930 let Inst{19-16} = 0b1111;
3931 let Inst{15-8} = 0b10000000;
3932 let Inst{7-4} = 0b1111;
3933 let Inst{3-0} = opt;
3936 // Secure Monitor Call is a system instruction.
3937 // Option = Inst{19-16}
3938 let isCall = 1, Uses = [SP] in
3939 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3940 []>, Requires<[IsThumb2, HasTrustZone]> {
3941 let Inst{31-27} = 0b11110;
3942 let Inst{26-20} = 0b1111111;
3943 let Inst{15-12} = 0b1000;
3946 let Inst{19-16} = opt;
3949 class T2DCPS<bits<2> opt, string opc>
3950 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
3951 let Inst{31-27} = 0b11110;
3952 let Inst{26-20} = 0b1111000;
3953 let Inst{19-16} = 0b1111;
3954 let Inst{15-12} = 0b1000;
3955 let Inst{11-2} = 0b0000000000;
3956 let Inst{1-0} = opt;
3959 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
3960 def t2DCPS2 : T2DCPS<0b10, "dcps2">;
3961 def t2DCPS3 : T2DCPS<0b11, "dcps3">;
3963 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3964 string opc, string asm, list<dag> pattern>
3965 : T2I<oops, iops, itin, opc, asm, pattern>,
3966 Requires<[IsThumb2,IsNotMClass]> {
3968 let Inst{31-25} = 0b1110100;
3969 let Inst{24-23} = Op;
3972 let Inst{20-16} = 0b01101;
3973 let Inst{15-5} = 0b11000000000;
3974 let Inst{4-0} = mode{4-0};
3977 // Store Return State is a system instruction.
3978 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3979 "srsdb", "\tsp!, $mode", []>;
3980 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3981 "srsdb","\tsp, $mode", []>;
3982 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3983 "srsia","\tsp!, $mode", []>;
3984 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3985 "srsia","\tsp, $mode", []>;
3988 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3989 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3991 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3992 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3994 // Return From Exception is a system instruction.
3995 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
3996 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3997 string opc, string asm, list<dag> pattern>
3998 : T2I<oops, iops, itin, opc, asm, pattern>,
3999 Requires<[IsThumb2,IsNotMClass]> {
4000 let Inst{31-20} = op31_20{11-0};
4003 let Inst{19-16} = Rn;
4004 let Inst{15-0} = 0xc000;
4007 def t2RFEDBW : T2RFE<0b111010000011,
4008 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
4009 [/* For disassembly only; pattern left blank */]>;
4010 def t2RFEDB : T2RFE<0b111010000001,
4011 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
4012 [/* For disassembly only; pattern left blank */]>;
4013 def t2RFEIAW : T2RFE<0b111010011011,
4014 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
4015 [/* For disassembly only; pattern left blank */]>;
4016 def t2RFEIA : T2RFE<0b111010011001,
4017 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
4018 [/* For disassembly only; pattern left blank */]>;
4020 // B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
4021 // Exception return instruction is "subs pc, lr, #imm".
4022 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
4023 def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
4024 "subs", "\tpc, lr, $imm",
4025 [(ARMintretflag imm0_255:$imm)]>,
4026 Requires<[IsThumb2,IsNotMClass]> {
4027 let Inst{31-8} = 0b111100111101111010001111;
4030 let Inst{7-0} = imm;
4033 // Hypervisor Call is a system instruction.
4035 def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>,
4036 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
4038 let Inst{31-20} = 0b111101111110;
4039 let Inst{19-16} = imm16{15-12};
4040 let Inst{15-12} = 0b1000;
4041 let Inst{11-0} = imm16{11-0};
4045 // Alias for HVC without the ".w" optional width specifier
4046 def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>;
4048 // ERET - Return from exception in Hypervisor mode.
4049 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
4050 // includes virtualization extensions.
4051 def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,
4052 Requires<[IsThumb2, HasVirtualization]>;
4054 //===----------------------------------------------------------------------===//
4055 // Non-Instruction Patterns
4058 // 32-bit immediate using movw + movt.
4059 // This is a single pseudo instruction to make it re-materializable.
4060 // FIXME: Remove this when we can do generalized remat.
4061 let isReMaterializable = 1, isMoveImm = 1 in
4062 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4063 [(set rGPR:$dst, (i32 imm:$src))]>,
4064 Requires<[IsThumb, UseMovt]>;
4066 // Pseudo instruction that combines movw + movt + add pc (if pic).
4067 // It also makes it possible to rematerialize the instructions.
4068 // FIXME: Remove this when we can do generalized remat and when machine licm
4069 // can properly the instructions.
4070 let isReMaterializable = 1 in {
4071 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
4073 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4074 Requires<[IsThumb, HasV8MBaseline, UseMovtInPic]>;
4078 def : T2Pat<(ARMWrapperPIC tglobaltlsaddr :$dst),
4079 (t2MOV_ga_pcrel tglobaltlsaddr:$dst)>,
4080 Requires<[IsThumb2, UseMovtInPic]>;
4081 def : T2Pat<(ARMWrapper tglobaltlsaddr:$dst),
4082 (t2MOVi32imm tglobaltlsaddr:$dst)>,
4083 Requires<[IsThumb2, UseMovt]>;
4085 // ConstantPool, GlobalAddress, and JumpTable
4086 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
4087 def : T2Pat<(ARMWrapper texternalsym :$dst), (t2MOVi32imm texternalsym :$dst)>,
4088 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
4089 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
4090 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
4092 def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>;
4094 // Pseudo instruction that combines ldr from constpool and add pc. This should
4095 // be expanded into two instructions late to allow if-conversion and
4097 let canFoldAsLoad = 1, isReMaterializable = 1 in
4098 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
4100 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
4102 Requires<[IsThumb2]>;
4104 // Pseudo isntruction that combines movs + predicated rsbmi
4105 // to implement integer ABS
4106 let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in {
4107 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
4108 NoItinerary, []>, Requires<[IsThumb2]>;
4111 //===----------------------------------------------------------------------===//
4112 // Coprocessor load/store -- for disassembly only
4114 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag> pattern>
4115 : T2I<oops, iops, NoItinerary, opc, asm, pattern> {
4116 let Inst{31-28} = op31_28;
4117 let Inst{27-25} = 0b110;
4120 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag> pattern> {
4121 def _OFFSET : T2CI<op31_28,
4122 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4123 asm, "\t$cop, $CRd, $addr", pattern> {
4127 let Inst{24} = 1; // P = 1
4128 let Inst{23} = addr{8};
4129 let Inst{22} = Dbit;
4130 let Inst{21} = 0; // W = 0
4131 let Inst{20} = load;
4132 let Inst{19-16} = addr{12-9};
4133 let Inst{15-12} = CRd;
4134 let Inst{11-8} = cop;
4135 let Inst{7-0} = addr{7-0};
4136 let DecoderMethod = "DecodeCopMemInstruction";
4138 def _PRE : T2CI<op31_28,
4139 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4140 asm, "\t$cop, $CRd, $addr!", []> {
4144 let Inst{24} = 1; // P = 1
4145 let Inst{23} = addr{8};
4146 let Inst{22} = Dbit;
4147 let Inst{21} = 1; // W = 1
4148 let Inst{20} = load;
4149 let Inst{19-16} = addr{12-9};
4150 let Inst{15-12} = CRd;
4151 let Inst{11-8} = cop;
4152 let Inst{7-0} = addr{7-0};
4153 let DecoderMethod = "DecodeCopMemInstruction";
4155 def _POST: T2CI<op31_28,
4156 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4157 postidx_imm8s4:$offset),
4158 asm, "\t$cop, $CRd, $addr, $offset", []> {
4163 let Inst{24} = 0; // P = 0
4164 let Inst{23} = offset{8};
4165 let Inst{22} = Dbit;
4166 let Inst{21} = 1; // W = 1
4167 let Inst{20} = load;
4168 let Inst{19-16} = addr;
4169 let Inst{15-12} = CRd;
4170 let Inst{11-8} = cop;
4171 let Inst{7-0} = offset{7-0};
4172 let DecoderMethod = "DecodeCopMemInstruction";
4174 def _OPTION : T2CI<op31_28, (outs),
4175 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4176 coproc_option_imm:$option),
4177 asm, "\t$cop, $CRd, $addr, $option", []> {
4182 let Inst{24} = 0; // P = 0
4183 let Inst{23} = 1; // U = 1
4184 let Inst{22} = Dbit;
4185 let Inst{21} = 0; // W = 0
4186 let Inst{20} = load;
4187 let Inst{19-16} = addr;
4188 let Inst{15-12} = CRd;
4189 let Inst{11-8} = cop;
4190 let Inst{7-0} = option;
4191 let DecoderMethod = "DecodeCopMemInstruction";
4195 let DecoderNamespace = "Thumb2CoProc" in {
4196 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]>;
4197 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;
4198 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4199 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4201 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]>;
4202 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;
4203 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4204 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4208 //===----------------------------------------------------------------------===//
4209 // Move between special register and ARM core register -- for disassembly only
4211 // Move to ARM core register from Special Register
4215 // A/R class can only move from CPSR or SPSR.
4216 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
4217 []>, Requires<[IsThumb2,IsNotMClass]> {
4219 let Inst{31-12} = 0b11110011111011111000;
4220 let Inst{11-8} = Rd;
4221 let Inst{7-0} = 0b00000000;
4224 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
4226 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
4227 []>, Requires<[IsThumb2,IsNotMClass]> {
4229 let Inst{31-12} = 0b11110011111111111000;
4230 let Inst{11-8} = Rd;
4231 let Inst{7-0} = 0b00000000;
4234 def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
4235 NoItinerary, "mrs", "\t$Rd, $banked", []>,
4236 Requires<[IsThumb, HasVirtualization]> {
4240 let Inst{31-21} = 0b11110011111;
4241 let Inst{20} = banked{5}; // R bit
4242 let Inst{19-16} = banked{3-0};
4243 let Inst{15-12} = 0b1000;
4244 let Inst{11-8} = Rd;
4245 let Inst{7-5} = 0b001;
4246 let Inst{4} = banked{4};
4247 let Inst{3-0} = 0b0000;
4253 // This MRS has a mask field in bits 7-0 and can take more values than
4254 // the A/R class (a full msr_mask).
4255 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,
4256 "mrs", "\t$Rd, $SYSm", []>,
4257 Requires<[IsThumb,IsMClass]> {
4260 let Inst{31-12} = 0b11110011111011111000;
4261 let Inst{11-8} = Rd;
4262 let Inst{7-0} = SYSm;
4264 let Unpredictable{20-16} = 0b11111;
4265 let Unpredictable{13} = 0b1;
4269 // Move from ARM core register to Special Register
4273 // No need to have both system and application versions, the encodings are the
4274 // same and the assembly parser has no way to distinguish between them. The mask
4275 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4276 // the mask with the fields to be accessed in the special register.
4277 let Defs = [CPSR] in
4278 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
4279 NoItinerary, "msr", "\t$mask, $Rn", []>,
4280 Requires<[IsThumb2,IsNotMClass]> {
4283 let Inst{31-21} = 0b11110011100;
4284 let Inst{20} = mask{4}; // R Bit
4285 let Inst{19-16} = Rn;
4286 let Inst{15-12} = 0b1000;
4287 let Inst{11-8} = mask{3-0};
4291 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
4292 // separate encoding (distinguished by bit 5.
4293 def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn),
4294 NoItinerary, "msr", "\t$banked, $Rn", []>,
4295 Requires<[IsThumb, HasVirtualization]> {
4299 let Inst{31-21} = 0b11110011100;
4300 let Inst{20} = banked{5}; // R bit
4301 let Inst{19-16} = Rn;
4302 let Inst{15-12} = 0b1000;
4303 let Inst{11-8} = banked{3-0};
4304 let Inst{7-5} = 0b001;
4305 let Inst{4} = banked{4};
4306 let Inst{3-0} = 0b0000;
4312 // Move from ARM core register to Special Register
4313 let Defs = [CPSR] in
4314 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
4315 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
4316 Requires<[IsThumb,IsMClass]> {
4319 let Inst{31-21} = 0b11110011100;
4321 let Inst{19-16} = Rn;
4322 let Inst{15-12} = 0b1000;
4323 let Inst{11-10} = SYSm{11-10};
4324 let Inst{9-8} = 0b00;
4325 let Inst{7-0} = SYSm{7-0};
4327 let Unpredictable{20} = 0b1;
4328 let Unpredictable{13} = 0b1;
4329 let Unpredictable{9-8} = 0b11;
4333 //===----------------------------------------------------------------------===//
4334 // Move between coprocessor and ARM core register
4337 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4339 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4341 let Inst{27-24} = 0b1110;
4342 let Inst{20} = direction;
4352 let Inst{15-12} = Rt;
4353 let Inst{11-8} = cop;
4354 let Inst{23-21} = opc1;
4355 let Inst{7-5} = opc2;
4356 let Inst{3-0} = CRm;
4357 let Inst{19-16} = CRn;
4359 let DecoderNamespace = "Thumb2CoProc";
4362 class t2MovRRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4363 list<dag> pattern = []>
4364 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4365 let Inst{27-24} = 0b1100;
4366 let Inst{23-21} = 0b010;
4367 let Inst{20} = direction;
4375 let Inst{15-12} = Rt;
4376 let Inst{19-16} = Rt2;
4377 let Inst{11-8} = cop;
4378 let Inst{7-4} = opc1;
4379 let Inst{3-0} = CRm;
4381 let DecoderNamespace = "Thumb2CoProc";
4384 /* from ARM core register to coprocessor */
4385 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
4387 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4388 c_imm:$CRm, imm0_7:$opc2),
4389 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,
4390 timm:$CRm, timm:$opc2)]>,
4391 ComplexDeprecationPredicate<"MCR">;
4392 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4393 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4394 c_imm:$CRm, 0, pred:$p)>;
4395 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
4396 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4397 c_imm:$CRm, imm0_7:$opc2),
4398 [(int_arm_mcr2 timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,
4399 timm:$CRm, timm:$opc2)]> {
4400 let Predicates = [IsThumb2, PreV8];
4402 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4403 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4404 c_imm:$CRm, 0, pred:$p)>;
4406 /* from coprocessor to ARM core register */
4407 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
4408 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4409 c_imm:$CRm, imm0_7:$opc2), []>;
4410 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4411 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4412 c_imm:$CRm, 0, pred:$p)>;
4414 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4415 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4416 c_imm:$CRm, imm0_7:$opc2), []> {
4417 let Predicates = [IsThumb2, PreV8];
4419 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4420 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4421 c_imm:$CRm, 0, pred:$p)>;
4423 def : T2v6Pat<(int_arm_mrc timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2),
4424 (t2MRC p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>;
4426 def : T2v6Pat<(int_arm_mrc2 timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2),
4427 (t2MRC2 p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>;
4430 /* from ARM core register to coprocessor */
4431 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs),
4432 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4434 [(int_arm_mcrr timm:$cop, timm:$opc1, GPR:$Rt, GPR:$Rt2,
4436 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, (outs),
4437 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4439 [(int_arm_mcrr2 timm:$cop, timm:$opc1, GPR:$Rt,
4440 GPR:$Rt2, timm:$CRm)]> {
4441 let Predicates = [IsThumb2, PreV8];
4444 /* from coprocessor to ARM core register */
4445 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),
4446 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)>;
4448 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),
4449 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)> {
4450 let Predicates = [IsThumb2, PreV8];
4453 //===----------------------------------------------------------------------===//
4454 // Other Coprocessor Instructions.
4457 def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4458 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4459 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4460 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn,
4461 timm:$CRm, timm:$opc2)]> {
4462 let Inst{27-24} = 0b1110;
4471 let Inst{3-0} = CRm;
4473 let Inst{7-5} = opc2;
4474 let Inst{11-8} = cop;
4475 let Inst{15-12} = CRd;
4476 let Inst{19-16} = CRn;
4477 let Inst{23-20} = opc1;
4479 let Predicates = [IsThumb2, PreV8];
4480 let DecoderNamespace = "Thumb2CoProc";
4483 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4484 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4485 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4486 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn,
4487 timm:$CRm, timm:$opc2)]> {
4488 let Inst{27-24} = 0b1110;
4497 let Inst{3-0} = CRm;
4499 let Inst{7-5} = opc2;
4500 let Inst{11-8} = cop;
4501 let Inst{15-12} = CRd;
4502 let Inst{19-16} = CRn;
4503 let Inst{23-20} = opc1;
4505 let Predicates = [IsThumb2, PreV8];
4506 let DecoderNamespace = "Thumb2CoProc";
4511 //===----------------------------------------------------------------------===//
4512 // ARMv8.1 Privilege Access Never extension
4516 def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,
4517 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
4522 let Inst{2-0} = 0b000;
4524 let Unpredictable{4} = 0b1;
4525 let Unpredictable{2-0} = 0b111;
4528 //===----------------------------------------------------------------------===//
4529 // ARMv8-M Security Extensions instructions
4532 let hasSideEffects = 1 in
4533 def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>,
4534 Requires<[Has8MSecExt]> {
4535 let Inst = 0xe97fe97f;
4538 class T2TT<bits<2> at, string asm, list<dag> pattern>
4539 : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn",
4544 let Inst{31-20} = 0b111010000100;
4545 let Inst{19-16} = Rn;
4546 let Inst{15-12} = 0b1111;
4547 let Inst{11-8} = Rt;
4549 let Inst{5-0} = 0b000000;
4551 let Unpredictable{5-0} = 0b111111;
4554 def t2TT : T2TT<0b00, "tt", []>, Requires<[IsThumb,Has8MSecExt]>;
4555 def t2TTT : T2TT<0b01, "ttt", []>, Requires<[IsThumb,Has8MSecExt]>;
4556 def t2TTA : T2TT<0b10, "tta", []>, Requires<[IsThumb,Has8MSecExt]>;
4557 def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>;
4559 //===----------------------------------------------------------------------===//
4560 // Non-Instruction Patterns
4563 // SXT/UXT with no rotate
4564 let AddedComplexity = 16 in {
4565 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
4566 Requires<[IsThumb2]>;
4567 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
4568 Requires<[IsThumb2]>;
4569 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
4570 Requires<[HasDSP, IsThumb2]>;
4571 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
4572 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4573 Requires<[HasDSP, IsThumb2]>;
4574 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
4575 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4576 Requires<[HasDSP, IsThumb2]>;
4579 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
4580 Requires<[IsThumb2]>;
4581 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
4582 Requires<[IsThumb2]>;
4583 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
4584 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4585 Requires<[HasDSP, IsThumb2]>;
4586 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
4587 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4588 Requires<[HasDSP, IsThumb2]>;
4590 // Atomic load/store patterns
4591 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4592 (t2LDRBi12 t2addrmode_imm12:$addr)>;
4593 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4594 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
4595 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4596 (t2LDRBs t2addrmode_so_reg:$addr)>;
4597 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4598 (t2LDRHi12 t2addrmode_imm12:$addr)>;
4599 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4600 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
4601 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4602 (t2LDRHs t2addrmode_so_reg:$addr)>;
4603 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
4604 (t2LDRi12 t2addrmode_imm12:$addr)>;
4605 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
4606 (t2LDRi8 t2addrmode_negimm8:$addr)>;
4607 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
4608 (t2LDRs t2addrmode_so_reg:$addr)>;
4609 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
4610 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
4611 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
4612 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4613 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
4614 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
4615 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
4616 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
4617 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
4618 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4619 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
4620 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
4621 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
4622 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
4623 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4624 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4625 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4626 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4628 let AddedComplexity = 8, Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex] in {
4629 def : Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
4630 def : Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
4631 def : Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>;
4632 def : Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>;
4633 def : Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>;
4634 def : Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>;
4638 //===----------------------------------------------------------------------===//
4639 // Assembler aliases
4642 // Aliases for ADC without the ".w" optional width specifier.
4643 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4644 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4645 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4646 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4647 pred:$p, cc_out:$s)>;
4649 // Aliases for SBC without the ".w" optional width specifier.
4650 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4651 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4652 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4653 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4654 pred:$p, cc_out:$s)>;
4656 // Aliases for ADD without the ".w" optional width specifier.
4657 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4658 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
4660 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4661 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4662 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4663 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4664 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4665 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4666 pred:$p, cc_out:$s)>;
4667 // ... and with the destination and source register combined.
4668 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4669 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4670 def : t2InstAlias<"add${p} $Rdn, $imm",
4671 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4672 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4673 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4674 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4675 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4676 pred:$p, cc_out:$s)>;
4678 // add w/ negative immediates is just a sub.
4679 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
4680 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4682 def : t2InstSubst<"add${p} $Rd, $Rn, $imm",
4683 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4684 def : t2InstSubst<"add${s}${p} $Rdn, $imm",
4685 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4687 def : t2InstSubst<"add${p} $Rdn, $imm",
4688 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4690 def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
4691 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4693 def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",
4694 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4695 def : t2InstSubst<"add${s}${p}.w $Rdn, $imm",
4696 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4698 def : t2InstSubst<"addw${p} $Rdn, $imm",
4699 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4702 // Aliases for SUB without the ".w" optional width specifier.
4703 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4704 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4705 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4706 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4707 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4708 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4709 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4710 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4711 pred:$p, cc_out:$s)>;
4712 // ... and with the destination and source register combined.
4713 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4714 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4715 def : t2InstAlias<"sub${p} $Rdn, $imm",
4716 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4717 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4718 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4719 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4720 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4721 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4722 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4723 pred:$p, cc_out:$s)>;
4725 // Alias for compares without the ".w" optional width specifier.
4726 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4727 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4728 def : t2InstAlias<"teq${p} $Rn, $Rm",
4729 (t2TEQrr rGPR:$Rn, rGPR:$Rm, pred:$p)>;
4730 def : t2InstAlias<"tst${p} $Rn, $Rm",
4731 (t2TSTrr rGPR:$Rn, rGPR:$Rm, pred:$p)>;
4734 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4735 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4736 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4738 // Non-predicable aliases of a predicable DSB: the predicate is (14, 0) where
4739 // 14 = AL (always execute) and 0 = "instruction doesn't read the CPSR".
4740 def : InstAlias<"ssbb", (t2DSB 0x0, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
4741 def : InstAlias<"pssbb", (t2DSB 0x4, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
4743 // Armv8-R 'Data Full Barrier'
4744 def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>;
4746 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4748 def : t2InstAlias<"ldr${p} $Rt, $addr",
4749 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4750 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4751 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4752 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4753 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4754 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4755 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4756 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4757 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4759 def : t2InstAlias<"ldr${p} $Rt, $addr",
4760 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4761 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4762 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4763 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4764 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4765 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4766 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4767 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4768 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4770 def : t2InstAlias<"ldr${p} $Rt, $addr",
4771 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4772 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4773 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4774 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4775 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4776 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4777 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4778 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4779 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4781 // Alias for MVN with(out) the ".w" optional width specifier.
4782 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4783 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4784 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4785 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4786 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4787 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4789 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
4790 // input operands swapped when the shift amount is zero (i.e., unspecified).
4791 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4792 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4793 Requires<[HasDSP, IsThumb2]>;
4794 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4795 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
4796 Requires<[HasDSP, IsThumb2]>;
4798 // PUSH/POP aliases for STM/LDM
4799 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4800 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4801 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4802 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4804 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4805 def : t2InstAlias<"stm${p} $Rn, $regs",
4806 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4807 def : t2InstAlias<"stm${p} $Rn!, $regs",
4808 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4810 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4811 def : t2InstAlias<"ldm${p} $Rn, $regs",
4812 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4813 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4814 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4816 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4817 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4818 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4819 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4820 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4822 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4823 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4824 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4825 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4826 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4828 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4829 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4830 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4831 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4834 // Alias for RSB without the ".w" optional width specifier, and with optional
4835 // implied destination register.
4836 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4837 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4838 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4839 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4840 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4841 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4842 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4843 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4846 // SSAT/USAT optional shift operand.
4847 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4848 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4849 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4850 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4852 // STM w/o the .w suffix.
4853 def : t2InstAlias<"stm${p} $Rn, $regs",
4854 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4856 // Alias for STR, STRB, and STRH without the ".w" optional
4858 def : t2InstAlias<"str${p} $Rt, $addr",
4859 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4860 def : t2InstAlias<"strb${p} $Rt, $addr",
4861 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4862 def : t2InstAlias<"strh${p} $Rt, $addr",
4863 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4865 def : t2InstAlias<"str${p} $Rt, $addr",
4866 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4867 def : t2InstAlias<"strb${p} $Rt, $addr",
4868 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4869 def : t2InstAlias<"strh${p} $Rt, $addr",
4870 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4872 // Extend instruction optional rotate operand.
4873 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4874 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4875 Requires<[HasDSP, IsThumb2]>;
4876 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4877 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4878 Requires<[HasDSP, IsThumb2]>;
4879 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4880 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4881 Requires<[HasDSP, IsThumb2]>;
4882 def : InstAlias<"sxtb16${p} $Rd, $Rm",
4883 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
4884 Requires<[HasDSP, IsThumb2]>;
4886 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4887 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4888 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4889 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4890 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4891 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4892 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4893 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4895 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4896 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4897 Requires<[HasDSP, IsThumb2]>;
4898 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4899 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4900 Requires<[HasDSP, IsThumb2]>;
4901 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4902 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4903 Requires<[HasDSP, IsThumb2]>;
4904 def : InstAlias<"uxtb16${p} $Rd, $Rm",
4905 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
4906 Requires<[HasDSP, IsThumb2]>;
4908 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4909 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4910 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4911 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4912 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4913 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4914 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4915 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4917 // Extend instruction w/o the ".w" optional width specifier.
4918 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4919 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4920 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4921 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
4922 Requires<[HasDSP, IsThumb2]>;
4923 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4924 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4926 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4927 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4928 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4929 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
4930 Requires<[HasDSP, IsThumb2]>;
4931 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4932 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4935 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4937 def : t2InstSubst<"mov${p} $Rd, $imm",
4938 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4939 def : t2InstSubst<"mvn${s}${p} $Rd, $imm",
4940 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
4941 // Same for AND <--> BIC
4942 def : t2InstSubst<"bic${s}${p} $Rd, $Rn, $imm",
4943 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4944 pred:$p, cc_out:$s)>;
4945 def : t2InstSubst<"bic${s}${p} $Rdn, $imm",
4946 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4947 pred:$p, cc_out:$s)>;
4948 def : t2InstSubst<"bic${s}${p}.w $Rd, $Rn, $imm",
4949 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4950 pred:$p, cc_out:$s)>;
4951 def : t2InstSubst<"bic${s}${p}.w $Rdn, $imm",
4952 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4953 pred:$p, cc_out:$s)>;
4954 def : t2InstSubst<"and${s}${p} $Rd, $Rn, $imm",
4955 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4956 pred:$p, cc_out:$s)>;
4957 def : t2InstSubst<"and${s}${p} $Rdn, $imm",
4958 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4959 pred:$p, cc_out:$s)>;
4960 def : t2InstSubst<"and${s}${p}.w $Rd, $Rn, $imm",
4961 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4962 pred:$p, cc_out:$s)>;
4963 def : t2InstSubst<"and${s}${p}.w $Rdn, $imm",
4964 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4965 pred:$p, cc_out:$s)>;
4967 def : t2InstSubst<"orn${s}${p} $Rd, $Rn, $imm",
4968 (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4969 pred:$p, cc_out:$s)>;
4970 def : t2InstSubst<"orn${s}${p} $Rdn, $imm",
4971 (t2ORRri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4972 pred:$p, cc_out:$s)>;
4973 def : t2InstSubst<"orr${s}${p} $Rd, $Rn, $imm",
4974 (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4975 pred:$p, cc_out:$s)>;
4976 def : t2InstSubst<"orr${s}${p} $Rdn, $imm",
4977 (t2ORNri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4978 pred:$p, cc_out:$s)>;
4979 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4980 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
4981 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4982 pred:$p, cc_out:$s)>;
4983 def : t2InstSubst<"add${s}${p} $Rd, $imm",
4984 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4985 pred:$p, cc_out:$s)>;
4986 // Same for CMP <--> CMN via t2_so_imm_neg
4987 def : t2InstSubst<"cmp${p} $Rd, $imm",
4988 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4989 def : t2InstSubst<"cmn${p} $Rd, $imm",
4990 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4993 // Wide 'mul' encoding can be specified with only two operands.
4994 def : t2InstAlias<"mul${p} $Rn, $Rm",
4995 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4997 // "neg" is and alias for "rsb rd, rn, #0"
4998 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4999 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
5001 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
5002 // these, unfortunately.
5003 // FIXME: LSL #0 in the shift should allow SP to be used as either the
5004 // source or destination (but not both).
5005 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
5006 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5007 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
5008 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5010 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
5011 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5012 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
5013 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5015 // Aliases for the above with the .w qualifier
5016 def : t2InstAlias<"mov${p}.w $Rd, $shift",
5017 (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5018 def : t2InstAlias<"movs${p}.w $Rd, $shift",
5019 (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5020 def : t2InstAlias<"mov${p}.w $Rd, $shift",
5021 (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5022 def : t2InstAlias<"movs${p}.w $Rd, $shift",
5023 (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5025 // ADR w/o the .w suffix
5026 def : t2InstAlias<"adr${p} $Rd, $addr",
5027 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
5029 // LDR(literal) w/ alternate [pc, #imm] syntax.
5030 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
5031 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
5032 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
5033 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
5034 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
5035 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
5036 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
5037 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
5038 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
5039 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
5040 // Version w/ the .w suffix.
5041 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
5042 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>;
5043 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
5044 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
5045 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
5046 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
5047 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
5048 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
5049 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
5050 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
5052 def : t2InstAlias<"add${p} $Rd, pc, $imm",
5053 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
5055 // Pseudo instruction ldr Rt, =immediate
5057 : t2AsmPseudo<"ldr${p} $Rt, $immediate",
5058 (ins GPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
5059 // Version w/ the .w suffix.
5060 def : t2InstAlias<"ldr${p}.w $Rt, $immediate",
5061 (t2LDRConstPool GPRnopc:$Rt,
5062 const_pool_asm_imm:$immediate, pred:$p)>;
5064 // PLD/PLDW/PLI with alternate literal form.
5065 def : t2InstAlias<"pld${p} $addr",
5066 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
5067 def : InstAlias<"pli${p} $addr",
5068 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
5069 Requires<[IsThumb2,HasV7]>;
5072 //===----------------------------------------------------------------------===//
5073 // ARMv8.1m instructions
5076 class V8_1MI<dag oops, dag iops, AddrMode am, InstrItinClass itin, string asm,
5077 string ops, string cstr, list<dag> pattern>
5078 : Thumb2XI<oops, iops, am, 4, itin, !strconcat(asm, "\t", ops), cstr,
5080 Requires<[HasV8_1MMainline]>;
5082 def t2CLRM : V8_1MI<(outs),
5083 (ins pred:$p, reglist_with_apsr:$regs, variable_ops),
5084 AddrModeNone, NoItinerary, "clrm", "${p}\t$regs", "", []> {
5087 let Inst{31-16} = 0b1110100010011111;
5088 let Inst{15-14} = regs{15-14};
5090 let Inst{12-0} = regs{12-0};
5093 class t2BF<dag iops, string asm, string ops>
5094 : V8_1MI<(outs ), iops, AddrModeNone, NoItinerary, asm, ops, "", []> {
5096 let Inst{31-27} = 0b11110;
5097 let Inst{15-14} = 0b11;
5101 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5104 def t2BF_LabelPseudo
5105 : t2PseudoInst<(outs ), (ins pclabel:$cp), 0, NoItinerary, []> {
5106 let isTerminator = 1;
5107 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5108 let hasNoSchedulingInfo = 1;
5111 def t2BFi : t2BF<(ins bflabel_u4:$b_label, bflabel_s16:$label, pred:$p),
5112 !strconcat("bf", "${p}"), "$b_label, $label"> {
5116 let Inst{26-23} = b_label{3-0};
5117 let Inst{22-21} = 0b10;
5118 let Inst{20-16} = label{15-11};
5120 let Inst{11} = label{0};
5121 let Inst{10-1} = label{10-1};
5124 def t2BFic : t2BF<(ins bflabel_u4:$b_label, bflabel_s12:$label,
5125 bfafter_target:$ba_label, pred_noal:$bcond), "bfcsel",
5126 "$b_label, $label, $ba_label, $bcond"> {
5132 let Inst{26-23} = b_label{3-0};
5134 let Inst{21-18} = bcond{3-0};
5135 let Inst{17} = ba_label{0};
5136 let Inst{16} = label{11};
5138 let Inst{11} = label{0};
5139 let Inst{10-1} = label{10-1};
5142 def t2BFr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
5143 !strconcat("bfx", "${p}"), "$b_label, $Rn"> {
5147 let Inst{26-23} = b_label{3-0};
5148 let Inst{22-20} = 0b110;
5149 let Inst{19-16} = Rn{3-0};
5150 let Inst{13-1} = 0b1000000000000;
5153 def t2BFLi : t2BF<(ins bflabel_u4:$b_label, bflabel_s18:$label, pred:$p),
5154 !strconcat("bfl", "${p}"), "$b_label, $label"> {
5158 let Inst{26-23} = b_label{3-0};
5159 let Inst{22-16} = label{17-11};
5161 let Inst{11} = label{0};
5162 let Inst{10-1} = label{10-1};
5165 def t2BFLr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
5166 !strconcat("bflx", "${p}"), "$b_label, $Rn"> {
5170 let Inst{26-23} = b_label{3-0};
5171 let Inst{22-20} = 0b111;
5172 let Inst{19-16} = Rn{3-0};
5173 let Inst{13-1} = 0b1000000000000;
5176 class t2LOL<dag oops, dag iops, string asm, string ops>
5177 : V8_1MI<oops, iops, AddrModeNone, NoItinerary, asm, ops, "", [] > {
5178 let Inst{31-23} = 0b111100000;
5179 let Inst{15-14} = 0b11;
5182 let isTerminator = 1;
5183 let DecoderMethod = "DecodeLOLoop";
5184 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5187 let isNotDuplicable = 1 in {
5188 def t2WLS : t2LOL<(outs GPRlr:$LR),
5189 (ins rGPR:$Rn, wlslabel_u11:$label),
5190 "wls", "$LR, $Rn, $label"> {
5193 let Inst{22-20} = 0b100;
5194 let Inst{19-16} = Rn{3-0};
5195 let Inst{13-12} = 0b00;
5196 let Inst{11} = label{0};
5197 let Inst{10-1} = label{10-1};
5198 let usesCustomInserter = 1;
5201 def t2DLS : t2LOL<(outs GPRlr:$LR), (ins rGPR:$Rn),
5202 "dls", "$LR, $Rn"> {
5205 let isTerminator = 0;
5206 let Inst{22-20} = 0b100;
5207 let Inst{19-16} = Rn{3-0};
5208 let Inst{13-1} = 0b1000000000000;
5209 let usesCustomInserter = 1;
5212 def t2LEUpdate : t2LOL<(outs GPRlr:$LRout),
5213 (ins GPRlr:$LRin, lelabel_u11:$label),
5214 "le", "$LRin, $label"> {
5216 let Inst{22-16} = 0b0001111;
5217 let Inst{13-12} = 0b00;
5218 let Inst{11} = label{0};
5219 let Inst{10-1} = label{10-1};
5220 let usesCustomInserter = 1;
5223 def t2LE : t2LOL<(outs ), (ins lelabel_u11:$label), "le", "$label"> {
5225 let Inst{22-16} = 0b0101111;
5226 let Inst{13-12} = 0b00;
5227 let Inst{11} = label{0};
5228 let Inst{10-1} = label{10-1};
5232 t2PseudoInst<(outs), (ins rGPR:$elts), 4, IIC_Br,
5233 [(int_set_loop_iterations rGPR:$elts)]>, Sched<[WriteBr]>;
5236 t2PseudoInst<(outs GPRlr:$Rm), (ins GPRlr:$Rn, imm0_7:$size),
5237 4, IIC_Br, []>, Sched<[WriteBr]>;
5239 let isBranch = 1, isTerminator = 1, hasSideEffects = 1, Defs = [CPSR] in {
5240 // Set WhileLoopStart and LoopEnd to occupy 8 bytes because they may
5241 // get converted into t2CMP and t2Bcc.
5242 def t2WhileLoopStart :
5243 t2PseudoInst<(outs),
5244 (ins rGPR:$elts, brtarget:$target),
5249 t2PseudoInst<(outs), (ins GPRlr:$elts, brtarget:$target),
5250 8, IIC_Br, []>, Sched<[WriteBr]>;
5252 } // end isBranch, isTerminator, hasSideEffects
5254 } // end isNotDuplicable
5256 class CS<string iname, bits<4> opcode, list<dag> pattern=[]>
5257 : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond),
5258 AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> {
5264 let Inst{31-20} = 0b111010100101;
5265 let Inst{19-16} = Rn{3-0};
5266 let Inst{15-12} = opcode;
5267 let Inst{11-8} = Rd{3-0};
5268 let Inst{7-4} = fcond{3-0};
5269 let Inst{3-0} = Rm{3-0};
5274 def t2CSEL : CS<"csel", 0b1000>;
5275 def t2CSINC : CS<"csinc", 0b1001>;
5276 def t2CSINV : CS<"csinv", 0b1010>;
5277 def t2CSNEG : CS<"csneg", 0b1011>;
5279 let Predicates = [HasV8_1MMainline] in {
5280 def : T2Pat<(ARMcsinc GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm),
5281 (t2CSINC GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
5282 def : T2Pat<(ARMcsinv GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm),
5283 (t2CSINV GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
5284 def : T2Pat<(ARMcsneg GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm),
5285 (t2CSNEG GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
5287 multiclass ModifiedV8_1CSEL<Instruction Insn, dag modvalue> {
5288 def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, cmovpred:$imm),
5289 (Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
5290 def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, cmovpred:$imm),
5291 (Insn GPRwithZR:$tval, GPRwithZR:$fval,
5292 (i32 (inv_cond_XFORM imm:$imm)))>;
5294 defm : ModifiedV8_1CSEL<t2CSINC, (add rGPR:$fval, 1)>;
5295 defm : ModifiedV8_1CSEL<t2CSINV, (xor rGPR:$fval, -1)>;
5296 defm : ModifiedV8_1CSEL<t2CSNEG, (sub 0, rGPR:$fval)>;
5300 let Predicates = [HasV8_1MMainline] in {
5301 def : InstAlias<"csetm\t$Rd, $fcond",
5302 (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
5304 def : InstAlias<"cset\t$Rd, $fcond",
5305 (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
5307 def : InstAlias<"cinc\t$Rd, $Rn, $fcond",
5308 (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
5310 def : InstAlias<"cinv\t$Rd, $Rn, $fcond",
5311 (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
5313 def : InstAlias<"cneg\t$Rd, $Rn, $fcond",
5314 (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;