1 // WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*-
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// WebAssembly Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // WebAssembly Instruction Predicate Definitions.
16 //===----------------------------------------------------------------------===//
18 def IsPIC : Predicate<"TM.isPositionIndependent()">;
19 def IsNotPIC : Predicate<"!TM.isPositionIndependent()">;
21 def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
23 def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
26 Predicate<"Subtarget->hasSIMD128()">,
27 AssemblerPredicate<"FeatureSIMD128", "simd128">;
29 def HasUnimplementedSIMD128 :
30 Predicate<"Subtarget->hasUnimplementedSIMD128()">,
31 AssemblerPredicate<"FeatureUnimplementedSIMD128", "unimplemented-simd128">;
34 Predicate<"Subtarget->hasAtomics()">,
35 AssemblerPredicate<"FeatureAtomics", "atomics">;
38 Predicate<"Subtarget->hasMultivalue()">,
39 AssemblerPredicate<"FeatureMultivalue", "multivalue">;
41 def HasNontrappingFPToInt :
42 Predicate<"Subtarget->hasNontrappingFPToInt()">,
43 AssemblerPredicate<"FeatureNontrappingFPToInt", "nontrapping-fptoint">;
45 def NotHasNontrappingFPToInt :
46 Predicate<"!Subtarget->hasNontrappingFPToInt()">,
47 AssemblerPredicate<"!FeatureNontrappingFPToInt", "nontrapping-fptoint">;
50 Predicate<"Subtarget->hasSignExt()">,
51 AssemblerPredicate<"FeatureSignExt", "sign-ext">;
54 Predicate<"Subtarget->hasTailCall()">,
55 AssemblerPredicate<"FeatureTailCall", "tail-call">;
57 def HasExceptionHandling :
58 Predicate<"Subtarget->hasExceptionHandling()">,
59 AssemblerPredicate<"FeatureExceptionHandling", "exception-handling">;
62 Predicate<"Subtarget->hasBulkMemory()">,
63 AssemblerPredicate<"FeatureBulkMemory", "bulk-memory">;
65 //===----------------------------------------------------------------------===//
66 // WebAssembly-specific DAG Node Types.
67 //===----------------------------------------------------------------------===//
69 def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
71 def SDT_WebAssemblyCallSeqEnd :
72 SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
73 def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
74 def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>;
75 def SDT_WebAssemblyBrTable : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
76 def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
77 def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>;
78 def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
80 def SDT_WebAssemblyWrapperPIC : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
82 def SDT_WebAssemblyThrow : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
84 //===----------------------------------------------------------------------===//
85 // WebAssembly-specific DAG Nodes.
86 //===----------------------------------------------------------------------===//
88 def WebAssemblycallseq_start :
89 SDNode<"ISD::CALLSEQ_START", SDT_WebAssemblyCallSeqStart,
90 [SDNPHasChain, SDNPOutGlue]>;
91 def WebAssemblycallseq_end :
92 SDNode<"ISD::CALLSEQ_END", SDT_WebAssemblyCallSeqEnd,
93 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
94 def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0",
96 [SDNPHasChain, SDNPVariadic]>;
97 def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1",
99 [SDNPHasChain, SDNPVariadic]>;
100 def WebAssemblyretcall : SDNode<"WebAssemblyISD::RET_CALL",
101 SDT_WebAssemblyCall0,
102 [SDNPHasChain, SDNPVariadic]>;
103 def WebAssemblybr_table : SDNode<"WebAssemblyISD::BR_TABLE",
104 SDT_WebAssemblyBrTable,
105 [SDNPHasChain, SDNPVariadic]>;
106 def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
107 SDT_WebAssemblyArgument>;
108 def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",
109 SDT_WebAssemblyReturn,
110 [SDNPHasChain, SDNPVariadic]>;
111 def WebAssemblywrapper : SDNode<"WebAssemblyISD::Wrapper",
112 SDT_WebAssemblyWrapper>;
113 def WebAssemblywrapperPIC : SDNode<"WebAssemblyISD::WrapperPIC",
114 SDT_WebAssemblyWrapperPIC>;
115 def WebAssemblythrow : SDNode<"WebAssemblyISD::THROW", SDT_WebAssemblyThrow,
116 [SDNPHasChain, SDNPVariadic]>;
118 //===----------------------------------------------------------------------===//
119 // WebAssembly-specific Operands.
120 //===----------------------------------------------------------------------===//
122 // Default Operand has AsmOperandClass "Imm" which is for integers (and
123 // symbols), so specialize one for floats:
124 def FPImmAsmOperand : AsmOperandClass {
126 let PredicateMethod = "isFPImm";
129 class FPOperand<ValueType ty> : Operand<ty> {
130 AsmOperandClass ParserMatchClass = FPImmAsmOperand;
133 let OperandNamespace = "WebAssembly" in {
135 let OperandType = "OPERAND_BASIC_BLOCK" in
136 def bb_op : Operand<OtherVT>;
138 let OperandType = "OPERAND_LOCAL" in
139 def local_op : Operand<i32>;
141 let OperandType = "OPERAND_GLOBAL" in
142 def global_op : Operand<i32>;
144 let OperandType = "OPERAND_I32IMM" in
145 def i32imm_op : Operand<i32>;
147 let OperandType = "OPERAND_I64IMM" in
148 def i64imm_op : Operand<i64>;
150 let OperandType = "OPERAND_F32IMM" in
151 def f32imm_op : FPOperand<f32>;
153 let OperandType = "OPERAND_F64IMM" in
154 def f64imm_op : FPOperand<f64>;
156 let OperandType = "OPERAND_VEC_I8IMM" in
157 def vec_i8imm_op : Operand<i32>;
159 let OperandType = "OPERAND_VEC_I16IMM" in
160 def vec_i16imm_op : Operand<i32>;
162 let OperandType = "OPERAND_VEC_I32IMM" in
163 def vec_i32imm_op : Operand<i32>;
165 let OperandType = "OPERAND_VEC_I64IMM" in
166 def vec_i64imm_op : Operand<i64>;
168 let OperandType = "OPERAND_FUNCTION32" in
169 def function32_op : Operand<i32>;
171 let OperandType = "OPERAND_OFFSET32" in
172 def offset32_op : Operand<i32>;
174 let OperandType = "OPERAND_P2ALIGN" in {
175 def P2Align : Operand<i32> {
176 let PrintMethod = "printWebAssemblyP2AlignOperand";
179 let OperandType = "OPERAND_EVENT" in
180 def event_op : Operand<i32>;
182 } // OperandType = "OPERAND_P2ALIGN"
184 let OperandType = "OPERAND_SIGNATURE" in
185 def Signature : Operand<i32> {
186 let PrintMethod = "printWebAssemblySignatureOperand";
189 let OperandType = "OPERAND_TYPEINDEX" in
190 def TypeIndex : Operand<i32>;
192 } // OperandNamespace = "WebAssembly"
194 //===----------------------------------------------------------------------===//
195 // WebAssembly Register to Stack instruction mapping
196 //===----------------------------------------------------------------------===//
199 def getStackOpcode : InstrMapping {
200 let FilterClass = "StackRel";
201 let RowFields = ["BaseName"];
202 let ColFields = ["StackBased"];
203 let KeyCol = ["false"];
204 let ValueCols = [["true"]];
207 //===----------------------------------------------------------------------===//
208 // WebAssembly Instruction Format Definitions.
209 //===----------------------------------------------------------------------===//
211 include "WebAssemblyInstrFormats.td"
213 //===----------------------------------------------------------------------===//
214 // Additional instructions.
215 //===----------------------------------------------------------------------===//
217 multiclass ARGUMENT<WebAssemblyRegClass reg, ValueType vt> {
218 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = []<Register>,
219 Uses = [ARGUMENTS] in
221 I<(outs reg:$res), (ins i32imm:$argno), (outs), (ins i32imm:$argno),
222 [(set (vt reg:$res), (WebAssemblyargument timm:$argno))]>;
224 defm "": ARGUMENT<I32, i32>;
225 defm "": ARGUMENT<I64, i64>;
226 defm "": ARGUMENT<F32, f32>;
227 defm "": ARGUMENT<F64, f64>;
228 defm "": ARGUMENT<EXNREF, exnref>;
230 // local.get and local.set are not generated by instruction selection; they
231 // are implied by virtual register uses and defs.
232 multiclass LOCAL<WebAssemblyRegClass vt> {
233 let hasSideEffects = 0 in {
234 // COPY is not an actual instruction in wasm, but since we allow local.get and
235 // local.set to be implicit during most of codegen, we can have a COPY which
236 // is actually a no-op because all the work is done in the implied local.get
237 // and local.set. COPYs are eliminated (and replaced with
238 // local.get/local.set) in the ExplicitLocals pass.
239 let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
240 defm COPY_#vt : I<(outs vt:$res), (ins vt:$src), (outs), (ins), [],
241 "local.copy\t$res, $src", "local.copy">;
243 // TEE is similar to COPY, but writes two copies of its result. Typically
244 // this would be used to stackify one result and write the other result to a
246 let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
247 defm TEE_#vt : I<(outs vt:$res, vt:$also), (ins vt:$src), (outs), (ins), [],
248 "local.tee\t$res, $also, $src", "local.tee">;
250 // This is the actual local.get instruction in wasm. These are made explicit
251 // by the ExplicitLocals pass. It has mayLoad because it reads from a wasm
252 // local, which is a side effect not otherwise modeled in LLVM.
253 let mayLoad = 1, isAsCheapAsAMove = 1 in
254 defm LOCAL_GET_#vt : I<(outs vt:$res), (ins local_op:$local),
255 (outs), (ins local_op:$local), [],
256 "local.get\t$res, $local", "local.get\t$local", 0x20>;
258 // This is the actual local.set instruction in wasm. These are made explicit
259 // by the ExplicitLocals pass. It has mayStore because it writes to a wasm
260 // local, which is a side effect not otherwise modeled in LLVM.
261 let mayStore = 1, isAsCheapAsAMove = 1 in
262 defm LOCAL_SET_#vt : I<(outs), (ins local_op:$local, vt:$src),
263 (outs), (ins local_op:$local), [],
264 "local.set\t$local, $src", "local.set\t$local", 0x21>;
266 // This is the actual local.tee instruction in wasm. TEEs are turned into
267 // LOCAL_TEEs by the ExplicitLocals pass. It has mayStore for the same reason
269 let mayStore = 1, isAsCheapAsAMove = 1 in
270 defm LOCAL_TEE_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src),
271 (outs), (ins local_op:$local), [],
272 "local.tee\t$res, $local, $src", "local.tee\t$local",
275 // Unused values must be dropped in some contexts.
276 defm DROP_#vt : I<(outs), (ins vt:$src), (outs), (ins), [],
277 "drop\t$src", "drop", 0x1a>;
280 defm GLOBAL_GET_#vt : I<(outs vt:$res), (ins global_op:$local),
281 (outs), (ins global_op:$local), [],
282 "global.get\t$res, $local", "global.get\t$local",
286 defm GLOBAL_SET_#vt : I<(outs), (ins global_op:$local, vt:$src),
287 (outs), (ins global_op:$local), [],
288 "global.set\t$local, $src", "global.set\t$local",
291 } // hasSideEffects = 0
293 defm "" : LOCAL<I32>;
294 defm "" : LOCAL<I64>;
295 defm "" : LOCAL<F32>;
296 defm "" : LOCAL<F64>;
297 defm "" : LOCAL<V128>, Requires<[HasSIMD128]>;
298 defm "" : LOCAL<EXNREF>, Requires<[HasExceptionHandling]>;
300 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
301 defm CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm),
302 (outs), (ins i32imm_op:$imm),
303 [(set I32:$res, imm:$imm)],
304 "i32.const\t$res, $imm", "i32.const\t$imm", 0x41>;
305 defm CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm),
306 (outs), (ins i64imm_op:$imm),
307 [(set I64:$res, imm:$imm)],
308 "i64.const\t$res, $imm", "i64.const\t$imm", 0x42>;
309 defm CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm),
310 (outs), (ins f32imm_op:$imm),
311 [(set F32:$res, fpimm:$imm)],
312 "f32.const\t$res, $imm", "f32.const\t$imm", 0x43>;
313 defm CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm),
314 (outs), (ins f64imm_op:$imm),
315 [(set F64:$res, fpimm:$imm)],
316 "f64.const\t$res, $imm", "f64.const\t$imm", 0x44>;
317 } // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1
319 def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)),
320 (CONST_I32 tglobaladdr:$addr)>, Requires<[IsNotPIC]>;
322 def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)),
323 (GLOBAL_GET_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>;
325 def : Pat<(i32 (WebAssemblywrapperPIC tglobaladdr:$addr)),
326 (CONST_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>;
328 def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)),
329 (GLOBAL_GET_I32 texternalsym:$addr)>, Requires<[IsPIC]>;
331 def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)),
332 (CONST_I32 texternalsym:$addr)>, Requires<[IsNotPIC]>;
334 def : Pat<(i32 (WebAssemblywrapper mcsym:$sym)), (CONST_I32 mcsym:$sym)>;
335 def : Pat<(i64 (WebAssemblywrapper mcsym:$sym)), (CONST_I64 mcsym:$sym)>;
337 //===----------------------------------------------------------------------===//
338 // Additional sets of instructions.
339 //===----------------------------------------------------------------------===//
341 include "WebAssemblyInstrMemory.td"
342 include "WebAssemblyInstrCall.td"
343 include "WebAssemblyInstrControl.td"
344 include "WebAssemblyInstrInteger.td"
345 include "WebAssemblyInstrConv.td"
346 include "WebAssemblyInstrFloat.td"
347 include "WebAssemblyInstrAtomics.td"
348 include "WebAssemblyInstrSIMD.td"
349 include "WebAssemblyInstrRef.td"
350 include "WebAssemblyInstrBulkMemory.td"