test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=WAVE64 %s
   3 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=WAVE32 %s
   4
   5 ---
   6 name: class_s32_vcc_sv
   7 legalized: true
   8 regBankSelected: true
   9 tracksRegLiveness: true
  10
  11 body: |
  12   bb.0:
  13     liveins: $sgpr0, $vgpr0
  14     ; WAVE64-LABEL: name: class_s32_vcc_sv
  15     ; WAVE64: liveins: $sgpr0, $vgpr0
  16     ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  17     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  18     ; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
  19     ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
  20     ; WAVE32-LABEL: name: class_s32_vcc_sv
  21     ; WAVE32: liveins: $sgpr0, $vgpr0
  22     ; WAVE32: $vcc_hi = IMPLICIT_DEF
  23     ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  24     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  25     ; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
  26     ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
  27     %0:sgpr(s32) = COPY $sgpr0
  28     %1:vgpr(s32) = COPY $vgpr0
  29     %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
  30     S_ENDPGM 0, implicit %2
  31 ...
  32
  33 ---
  34 name: class_s32_vcc_vs
  35 legalized: true
  36 regBankSelected: true
  37 tracksRegLiveness: true
  38
  39 body: |
  40   bb.0:
  41     liveins: $sgpr0, $vgpr0
  42     ; WAVE64-LABEL: name: class_s32_vcc_vs
  43     ; WAVE64: liveins: $sgpr0, $vgpr0
  44     ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  45     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
  46     ; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
  47     ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
  48     ; WAVE32-LABEL: name: class_s32_vcc_vs
  49     ; WAVE32: liveins: $sgpr0, $vgpr0
  50     ; WAVE32: $vcc_hi = IMPLICIT_DEF
  51     ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  52     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
  53     ; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
  54     ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
  55     %0:vgpr(s32) = COPY $vgpr0
  56     %1:sgpr(s32) = COPY $sgpr0
  57     %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
  58     S_ENDPGM 0, implicit %2
  59 ...
  60
  61 ---
  62 name: class_s32_vcc_vv
  63 legalized: true
  64 regBankSelected: true
  65 tracksRegLiveness: true
  66
  67 body: |
  68   bb.0:
  69     liveins: $vgpr0, $vgpr1
  70     ; WAVE64-LABEL: name: class_s32_vcc_vv
  71     ; WAVE64: liveins: $vgpr0, $vgpr1
  72     ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  73     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  74     ; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
  75     ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
  76     ; WAVE32-LABEL: name: class_s32_vcc_vv
  77     ; WAVE32: liveins: $vgpr0, $vgpr1
  78     ; WAVE32: $vcc_hi = IMPLICIT_DEF
  79     ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  80     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  81     ; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
  82     ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
  83     %0:vgpr(s32) = COPY $vgpr0
  84     %1:vgpr(s32) = COPY $vgpr1
  85     %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
  86     S_ENDPGM 0, implicit %2
  87 ...
  88
  89 ---
  90 name: class_s64_vcc_sv
  91 legalized: true
  92 regBankSelected: true
  93 tracksRegLiveness: true
  94
  95 body: |
  96   bb.0:
  97     liveins: $sgpr0_sgpr1, $vgpr0
  98     ; WAVE64-LABEL: name: class_s64_vcc_sv
  99     ; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
 100     ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 101     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 102     ; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
 103     ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
 104     ; WAVE32-LABEL: name: class_s64_vcc_sv
 105     ; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
 106     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 107     ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 108     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 109     ; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
 110     ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
 111     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 112     %1:vgpr(s32) = COPY $vgpr0
 113     %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
 114     S_ENDPGM 0, implicit %2
 115 ...
 116
 117 ---
 118 name: class_s64_vcc_vs
 119 legalized: true
 120 regBankSelected: true
 121 tracksRegLiveness: true
 122
 123 body: |
 124   bb.0:
 125     liveins: $sgpr0_sgpr1, $vgpr0
 126
 127     ; WAVE64-LABEL: name: class_s64_vcc_vs
 128     ; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
 129     ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 130     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
 131     ; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
 132     ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
 133     ; WAVE32-LABEL: name: class_s64_vcc_vs
 134     ; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
 135     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 136     ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 137     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
 138     ; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
 139     ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
 140     %0:vgpr(s64) = COPY $vgpr0_vgpr1
 141     %1:sgpr(s32) = COPY $sgpr0
 142     %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
 143     S_ENDPGM 0, implicit %2
 144 ...
 145
 146 ---
 147 name: class_s64_vcc_vv
 148 legalized: true
 149 regBankSelected: true
 150 tracksRegLiveness: true
 151
 152 body: |
 153   bb.0:
 154     liveins: $vgpr0_vgpr1, $vgpr2
 155
 156     ; WAVE64-LABEL: name: class_s64_vcc_vv
 157     ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2
 158     ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 159     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
 160     ; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
 161     ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
 162     ; WAVE32-LABEL: name: class_s64_vcc_vv
 163     ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2
 164     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 165     ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 166     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
 167     ; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
 168     ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
 169     %0:vgpr(s64) = COPY $vgpr0_vgpr1
 170     %1:vgpr(s32) = COPY $vgpr2
 171     %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
 172     S_ENDPGM 0, implicit %2
 173 ...