test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
   3 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
   4
   5 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*'  %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s
   6
   7 # SI-ERR-NOT: remark
   8 # SI-ERR: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:sgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_sv)
   9 # SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:sgpr(s32) (in function: class_s16_vcc_vs)
  10 # SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_vv)
  11 # SI-ERR-NOT: remark
  12
  13 ---
  14 name: class_s16_vcc_sv
  15 legalized: true
  16 regBankSelected: true
  17 tracksRegLiveness: true
  18
  19 body: |
  20   bb.0:
  21     liveins: $sgpr0, $vgpr0
  22     ; WAVE32-LABEL: name: class_s16_vcc_sv
  23     ; WAVE32: liveins: $sgpr0, $vgpr0
  24     ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  25     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  26     ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
  27     ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
  28     ; WAVE64-LABEL: name: class_s16_vcc_sv
  29     ; WAVE64: liveins: $sgpr0, $vgpr0
  30     ; WAVE64: $vcc_hi = IMPLICIT_DEF
  31     ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  32     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  33     ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
  34     ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
  35     %0:sgpr(s32) = COPY $sgpr0
  36     %1:vgpr(s32) = COPY $vgpr0
  37     %2:sgpr(s16) = G_TRUNC %0
  38     %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
  39     S_ENDPGM 0, implicit %4
  40 ...
  41
  42 ---
  43 name: class_s16_vcc_vs
  44 legalized: true
  45 regBankSelected: true
  46 tracksRegLiveness: true
  47
  48 body: |
  49   bb.0:
  50     liveins: $sgpr0, $vgpr0
  51     ; WAVE32-LABEL: name: class_s16_vcc_vs
  52     ; WAVE32: liveins: $sgpr0, $vgpr0
  53     ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  54     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
  55     ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
  56     ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
  57     ; WAVE64-LABEL: name: class_s16_vcc_vs
  58     ; WAVE64: liveins: $sgpr0, $vgpr0
  59     ; WAVE64: $vcc_hi = IMPLICIT_DEF
  60     ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  61     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
  62     ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
  63     ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
  64     %0:vgpr(s32) = COPY $vgpr0
  65     %1:sgpr(s32) = COPY $sgpr0
  66     %2:vgpr(s16) = G_TRUNC %0
  67     %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
  68     S_ENDPGM 0, implicit %4
  69 ...
  70
  71 ---
  72 name: class_s16_vcc_vv
  73 legalized: true
  74 regBankSelected: true
  75 tracksRegLiveness: true
  76
  77 body: |
  78   bb.0:
  79     liveins: $vgpr0, $vgpr1
  80     ; WAVE32-LABEL: name: class_s16_vcc_vv
  81     ; WAVE32: liveins: $vgpr0, $vgpr1
  82     ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  83     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  84     ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
  85     ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
  86     ; WAVE64-LABEL: name: class_s16_vcc_vv
  87     ; WAVE64: liveins: $vgpr0, $vgpr1
  88     ; WAVE64: $vcc_hi = IMPLICIT_DEF
  89     ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  90     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  91     ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
  92     ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
  93     %0:vgpr(s32) = COPY $vgpr0
  94     %1:vgpr(s32) = COPY $vgpr1
  95     %2:vgpr(s16) = G_TRUNC %0
  96     %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
  97     S_ENDPGM 0, implicit %4
  98 ...