1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s
5 # SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1:sgpr(s16) (in function: rsq_s16_vs)
6 # SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1:vgpr(s16) (in function: rsq_s16_vv)
11 tracksRegLiveness: true
17 ; CHECK-LABEL: name: rsq_s16_vs
18 ; CHECK: liveins: $sgpr0
19 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
20 ; CHECK: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $exec
21 ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]]
22 %0:sgpr(s32) = COPY $sgpr0
23 %1:sgpr(s16) = G_TRUNC %0
24 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1
25 S_ENDPGM 0, implicit %2
32 tracksRegLiveness: true
38 ; CHECK-LABEL: name: rsq_s16_vv
39 ; CHECK: liveins: $vgpr0
40 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
41 ; CHECK: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $exec
42 ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]]
43 %0:vgpr(s32) = COPY $vgpr0
44 %1:vgpr(s16) = G_TRUNC %0
45 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1
46 S_ENDPGM 0, implicit %2