test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
   3
   4 ---
   5
   6 name:            insert_s512_s32
   7 legalized:       true
   8 regBankSelected: true
   9
  10 body: |
  11   bb.0:
  12     ; CHECK-LABEL: name: insert_s512_s32
  13     ; CHECK: [[DEF:%[0-9]+]]:sreg_512 = IMPLICIT_DEF
  14     ; CHECK: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  15     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[DEF]], [[DEF1]], %subreg.sub0
  16     ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG]], [[DEF1]], %subreg.sub1
  17     ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG1]], [[DEF1]], %subreg.sub2
  18     ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG2]], [[DEF1]], %subreg.sub3
  19     ; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG3]], [[DEF1]], %subreg.sub4
  20     ; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG4]], [[DEF1]], %subreg.sub5
  21     ; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG5]], [[DEF1]], %subreg.sub6
  22     ; CHECK: [[INSERT_SUBREG7:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG6]], [[DEF1]], %subreg.sub7
  23     ; CHECK: [[INSERT_SUBREG8:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG7]], [[DEF1]], %subreg.sub8
  24     ; CHECK: [[INSERT_SUBREG9:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG8]], [[DEF1]], %subreg.sub9
  25     ; CHECK: [[INSERT_SUBREG10:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG9]], [[DEF1]], %subreg.sub10
  26     ; CHECK: [[INSERT_SUBREG11:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG10]], [[DEF1]], %subreg.sub11
  27     ; CHECK: [[INSERT_SUBREG12:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG11]], [[DEF1]], %subreg.sub12
  28     ; CHECK: [[INSERT_SUBREG13:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG12]], [[DEF1]], %subreg.sub13
  29     ; CHECK: [[INSERT_SUBREG14:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG13]], [[DEF1]], %subreg.sub14
  30     ; CHECK: [[INSERT_SUBREG15:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG14]], [[DEF1]], %subreg.sub15
  31     ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[INSERT_SUBREG15]]
  32     ; CHECK: SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
  33     %0:sgpr(s512) = G_IMPLICIT_DEF
  34     %1:sgpr(s32) = G_IMPLICIT_DEF
  35     %2:sgpr(s512) = G_INSERT %0:sgpr, %1:sgpr(s32), 0
  36     %3:sgpr(s512) = G_INSERT %2:sgpr, %1:sgpr(s32), 32
  37     %4:sgpr(s512) = G_INSERT %3:sgpr, %1:sgpr(s32), 64
  38     %5:sgpr(s512) = G_INSERT %4:sgpr, %1:sgpr(s32), 96
  39     %6:sgpr(s512) = G_INSERT %5:sgpr, %1:sgpr(s32), 128
  40     %7:sgpr(s512) = G_INSERT %6:sgpr, %1:sgpr(s32), 160
  41     %8:sgpr(s512) = G_INSERT %7:sgpr, %1:sgpr(s32), 192
  42     %9:sgpr(s512) = G_INSERT %8:sgpr, %1:sgpr(s32), 224
  43     %10:sgpr(s512) = G_INSERT %9:sgpr, %1:sgpr(s32), 256
  44     %11:sgpr(s512) = G_INSERT %10:sgpr, %1:sgpr(s32), 288
  45     %12:sgpr(s512) = G_INSERT %11:sgpr, %1:sgpr(s32), 320
  46     %13:sgpr(s512) = G_INSERT %12:sgpr, %1:sgpr(s32), 352
  47     %14:sgpr(s512) = G_INSERT %13:sgpr, %1:sgpr(s32), 384
  48     %15:sgpr(s512) = G_INSERT %14:sgpr, %1:sgpr(s32), 416
  49     %16:sgpr(s512) = G_INSERT %15:sgpr, %1:sgpr(s32), 448
  50     %17:sgpr(s512) = G_INSERT %16:sgpr, %1:sgpr(s32), 480
  51     $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %17:sgpr(s512)
  52     SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
  53
  54 ---
  55
  56 name:            insert_v_s64_v_s32_0
  57 legalized:       true
  58 regBankSelected: true
  59
  60 body: |
  61   bb.0:
  62     liveins:  $vgpr0_vgpr1, $vgpr2
  63     %0:vgpr(s64) = COPY $vgpr0_vgpr1
  64     %1:vgpr(s32) = COPY $vgpr2
  65     %2:vgpr(s64) = G_INSERT %0, %1, 0
  66     S_ENDPGM 0, implicit %2
  67 ...
  68
  69 ---
  70
  71 name:            insert_v_s64_v_s32_32
  72 legalized:       true
  73 regBankSelected: true
  74
  75 body: |
  76   bb.0:
  77     liveins:  $vgpr0_vgpr1, $vgpr2
  78     ; CHECK-LABEL: name: insert_v_s64_v_s32_32
  79     ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  80     ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  81     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
  82     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
  83     %0:vgpr(s64) = COPY $vgpr0_vgpr1
  84     %1:vgpr(s32) = COPY $vgpr2
  85     %2:vgpr(s64) = G_INSERT %0, %1, 32
  86     S_ENDPGM 0, implicit %2
  87 ...
  88
  89 ---
  90
  91 name:            insert_s_s64_s_s32_0
  92 legalized:       true
  93 regBankSelected: true
  94
  95 body: |
  96   bb.0:
  97     liveins:  $sgpr0_sgpr1, $sgpr2
  98     ; CHECK-LABEL: name: insert_s_s64_s_s32_0
  99     ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 100     ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
 101     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64_xexec = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
 102     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 103     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 104     %1:sgpr(s32) = COPY $sgpr2
 105     %2:sgpr(s64) = G_INSERT %0, %1, 0
 106     S_ENDPGM 0, implicit %2
 107 ...
 108
 109 ---
 110
 111 name:            insert_s_s64_s_s32_32
 112 legalized:       true
 113 regBankSelected: true
 114
 115 body: |
 116   bb.0:
 117     liveins:  $sgpr0_sgpr1, $sgpr2
 118     ; CHECK-LABEL: name: insert_s_s64_s_s32_32
 119     ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 120     ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
 121     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64_xexec = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
 122     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 123     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 124     %1:sgpr(s32) = COPY $sgpr2
 125     %2:sgpr(s64) = G_INSERT %0, %1, 32
 126     S_ENDPGM 0, implicit %2
 127 ...
 128
 129 ---
 130
 131 name:            insert_s_s64_v_s32_32
 132 legalized:       true
 133 regBankSelected: true
 134
 135 body: |
 136   bb.0:
 137     liveins:  $sgpr0_sgpr1, $vgpr0
 138     ; CHECK-LABEL: name: insert_s_s64_v_s32_32
 139     ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 140     ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
 141     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
 142     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 143     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 144     %1:vgpr(s32) = COPY $vgpr2
 145     %2:vgpr(s64) = G_INSERT %0, %1, 32
 146     S_ENDPGM 0, implicit %2
 147 ...
 148
 149 ---
 150
 151 name:            insert_v_s64_s_s32_32
 152 legalized:       true
 153 regBankSelected: true
 154
 155 body: |
 156   bb.0:
 157     liveins:  $vgpr0_vgpr1, $sgpr0
 158     ; CHECK-LABEL: name: insert_v_s64_s_s32_32
 159     ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 160     ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
 161     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
 162     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 163     %0:vgpr(s64) = COPY $vgpr0_vgpr1
 164     %1:sgpr(s32) = COPY $sgpr0
 165     %2:vgpr(s64) = G_INSERT %0, %1, 32
 166     S_ENDPGM 0, implicit %2
 167 ...
 168
 169 ---
 170
 171 name:            insert_v_s96_v_s64_0
 172 legalized:       true
 173 regBankSelected: true
 174
 175 body: |
 176   bb.0:
 177     liveins:  $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
 178     ; CHECK-LABEL: name: insert_v_s96_v_s64_0
 179     ; CHECK: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
 180     ; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
 181     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
 182     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 183     %0:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
 184     %1:vgpr(s64) = COPY $vgpr3_vgpr4
 185     %2:vgpr(s96) = G_INSERT %0, %1, 0
 186     S_ENDPGM 0, implicit %2
 187 ...
 188
 189 ---
 190
 191 name:            insert_v_s96_v_s64_32
 192 legalized:       true
 193 regBankSelected: true
 194
 195 body: |
 196   bb.0:
 197     liveins:  $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
 198     ; CHECK-LABEL: name: insert_v_s96_v_s64_32
 199     ; CHECK: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
 200     ; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
 201     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2
 202     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 203     %0:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
 204     %1:vgpr(s64) = COPY $vgpr3_vgpr4
 205     %2:vgpr(s96) = G_INSERT %0, %1, 32
 206     S_ENDPGM 0, implicit %2
 207 ...
 208
 209 ---
 210
 211 name:            insert_s_s96_s_s64_0
 212 legalized:       true
 213 regBankSelected: true
 214
 215 body: |
 216   bb.0:
 217     liveins:  $sgpr0_sgpr1_sgpr2, $sgpr4_sgpr5
 218     ; CHECK-LABEL: name: insert_s_s96_s_s64_0
 219     ; CHECK: [[COPY:%[0-9]+]]:sgpr_96_with_sub0_sub1 = COPY $sgpr0_sgpr1_sgpr2
 220     ; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
 221     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
 222     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 223     %0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
 224     %1:sgpr(s64) = COPY $sgpr4_sgpr5
 225     %2:sgpr(s96) = G_INSERT %0, %1, 0
 226     S_ENDPGM 0, implicit %2
 227 ...
 228
 229 ---
 230
 231 name:            insert_s_s96_s_s64_32
 232 legalized:       true
 233 regBankSelected: true
 234
 235 body: |
 236   bb.0:
 237     liveins:  $sgpr0_sgpr1_sgpr2, $sgpr4_sgpr5
 238     ; CHECK-LABEL: name: insert_s_s96_s_s64_32
 239     ; CHECK: [[COPY:%[0-9]+]]:sgpr_96_with_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2
 240     ; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
 241     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2
 242     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 243     %0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
 244     %1:sgpr(s64) = COPY $sgpr4_sgpr5
 245     %2:sgpr(s96) = G_INSERT %0, %1, 32
 246     S_ENDPGM 0, implicit %2
 247 ...
 248
 249 ---
 250
 251 name:            insert_s_s128_s_s64_0
 252 legalized:       true
 253 regBankSelected: true
 254
 255 body: |
 256   bb.0:
 257     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
 258     ; CHECK-LABEL: name: insert_s_s128_s_s64_0
 259     ; CHECK: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 260     ; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
 261     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
 262     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 263     %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 264     %1:sgpr(s64) = COPY $sgpr4_sgpr5
 265     %2:sgpr(s128) = G_INSERT %0, %1, 0
 266     S_ENDPGM 0, implicit %2
 267 ...
 268
 269 # ---
 270
 271 # name:            insert_s_s128_s_s64_32
 272 # legalized:       true
 273 # regBankSelected: true
 274
 275 # body: |
 276 #   bb.0:
 277 #     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
 278 #     %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 279 #     %1:sgpr(s64) = COPY $sgpr4_sgpr5
 280 #     %2:sgpr(s128) = G_INSERT %0, %1, 32
 281 #     S_ENDPGM 0, implicit %2
 282 # ...
 283
 284 ---
 285
 286 name:            insert_s_s128_s_s64_64
 287 legalized:       true
 288 regBankSelected: true
 289
 290 body: |
 291   bb.0:
 292     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
 293     ; CHECK-LABEL: name: insert_s_s128_s_s64_64
 294     ; CHECK: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 295     ; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
 296     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3
 297     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 298     %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 299     %1:sgpr(s64) = COPY $sgpr4_sgpr5
 300     %2:sgpr(s128) = G_INSERT %0, %1, 64
 301     S_ENDPGM 0, implicit %2
 302 ...
 303
 304 ---
 305
 306 name:            insert_s_v256_v_s64_96
 307 legalized:       true
 308 regBankSelected: true
 309
 310 body: |
 311   bb.0:
 312     liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9
 313     ; CHECK-LABEL: name: insert_s_v256_v_s64_96
 314     ; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 315     ; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9
 316     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4
 317     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 318     %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 319     %1:vgpr(s64) = COPY $vgpr8_vgpr9
 320     %2:vgpr(s256) = G_INSERT %0, %1, 96
 321     S_ENDPGM 0, implicit %2
 322 ...
 323
 324 ---
 325
 326 name:            insert_s_s256_s_s64_128
 327 legalized:       true
 328 regBankSelected: true
 329
 330 body: |
 331   bb.0:
 332     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
 333     ; CHECK-LABEL: name: insert_s_s256_s_s64_128
 334     ; CHECK: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 335     ; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
 336     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5
 337     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 338     %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 339     %1:sgpr(s64) = COPY $sgpr4_sgpr5
 340     %2:sgpr(s256) = G_INSERT %0, %1, 128
 341     S_ENDPGM 0, implicit %2
 342 ...
 343
 344 # ---
 345
 346 # name:            insert_s_s256_s_s64_160
 347 # legalized:       true
 348 # regBankSelected: true
 349
 350 # body: |
 351 #   bb.0:
 352 #     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
 353 #     %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 354 #     %1:sgpr(s64) = COPY $sgpr4_sgpr5
 355 #     %2:sgpr(s256) = G_INSERT %0, %1, 160
 356 #     S_ENDPGM 0, implicit %2
 357 # ...
 358
 359 ---
 360
 361 name:            insert_s_s128_s_s96_0
 362 legalized:       true
 363 regBankSelected: true
 364
 365 body: |
 366   bb.0:
 367     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr6_sgpr7_sgpr8
 368     ; CHECK-LABEL: name: insert_s_s128_s_s96_0
 369     ; CHECK: [[COPY:%[0-9]+]]:sgpr_128_with_sub0_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 370     ; CHECK: [[COPY1:%[0-9]+]]:sreg_96 = COPY $sgpr6_sgpr7_sgpr8
 371     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
 372     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 373     %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 374     %1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
 375     %2:sgpr(s128) = G_INSERT %0, %1, 0
 376     S_ENDPGM 0, implicit %2
 377 ...
 378
 379 ---
 380
 381 name:            insert_s_s128_s_s96_32
 382 legalized:       true
 383 regBankSelected: true
 384
 385 body: |
 386   bb.0:
 387     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr6_sgpr7_sgpr8
 388     ; CHECK-LABEL: name: insert_s_s128_s_s96_32
 389     ; CHECK: [[COPY:%[0-9]+]]:sgpr_128_with_sub1_sub2_sub3 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 390     ; CHECK: [[COPY1:%[0-9]+]]:sreg_96 = COPY $sgpr6_sgpr7_sgpr8
 391     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3
 392     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 393     %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 394     %1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
 395     %2:sgpr(s128) = G_INSERT %0, %1, 32
 396     S_ENDPGM 0, implicit %2
 397 ...
 398
 399 ---
 400
 401 name:            insert_s_s160_s_s96_0
 402 legalized:       true
 403 regBankSelected: true
 404
 405 body: |
 406   bb.0:
 407     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr6_sgpr7_sgpr8
 408     ; CHECK-LABEL: name: insert_s_s160_s_s96_0
 409     ; CHECK: [[COPY:%[0-9]+]]:sgpr_160_with_sub0_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
 410     ; CHECK: [[COPY1:%[0-9]+]]:sreg_96 = COPY $sgpr6_sgpr7_sgpr8
 411     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
 412     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 413     %0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
 414     %1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
 415     %2:sgpr(s160) = G_INSERT %0, %1, 0
 416     S_ENDPGM 0, implicit %2
 417 ...
 418
 419 ---
 420
 421 name:            insert_s_s160_s_s96_32
 422 legalized:       true
 423 regBankSelected: true
 424
 425 body: |
 426   bb.0:
 427     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr6_sgpr7_sgpr8
 428     ; CHECK-LABEL: name: insert_s_s160_s_s96_32
 429     ; CHECK: [[COPY:%[0-9]+]]:sgpr_160_with_sub1_sub2_sub3 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
 430     ; CHECK: [[COPY1:%[0-9]+]]:sreg_96 = COPY $sgpr6_sgpr7_sgpr8
 431     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3
 432     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 433     %0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
 434     %1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
 435     %2:sgpr(s160) = G_INSERT %0, %1, 32
 436     S_ENDPGM 0, implicit %2
 437 ...
 438
 439 ---
 440
 441 name:            insert_s_s160_s_s96_64
 442 legalized:       true
 443 regBankSelected: true
 444
 445 body: |
 446   bb.0:
 447     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr6_sgpr7_sgpr8
 448     ; CHECK-LABEL: name: insert_s_s160_s_s96_64
 449     ; CHECK: [[COPY:%[0-9]+]]:sgpr_160_with_sub2_sub3_sub4 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
 450     ; CHECK: [[COPY1:%[0-9]+]]:sreg_96 = COPY $sgpr6_sgpr7_sgpr8
 451     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3_sub4
 452     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 453     %0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
 454     %1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
 455     %2:sgpr(s160) = G_INSERT %0, %1, 64
 456     S_ENDPGM 0, implicit %2
 457 ...
 458
 459 ---
 460
 461 name:            insert_s_s256_s_s128_0
 462 legalized:       true
 463 regBankSelected: true
 464
 465 body: |
 466   bb.0:
 467     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11
 468
 469     ; CHECK-LABEL: name: insert_s_s256_s_s128_0
 470     ; CHECK: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 471     ; CHECK: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
 472     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2_sub3
 473     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 474     %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 475     %1:sgpr(s128) = COPY $sgpr8_sgpr9_sgpr10_sgpr11
 476     %2:sgpr(s256) = G_INSERT %0, %1, 0
 477     S_ENDPGM 0, implicit %2
 478 ...
 479
 480 ---
 481
 482 name:            insert_v_s256_v_s128_32
 483 legalized:       true
 484 regBankSelected: true
 485
 486 body: |
 487   bb.0:
 488     liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
 489
 490     ; CHECK-LABEL: name: insert_v_s256_v_s128_32
 491     ; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 492     ; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
 493     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3_sub4
 494     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 495     %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 496     %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
 497     %2:vgpr(s256) = G_INSERT %0, %1, 32
 498     S_ENDPGM 0, implicit %2
 499 ...
 500
 501 ---
 502
 503 name:            insert_v_s256_v_s128_64
 504 legalized:       true
 505 regBankSelected: true
 506
 507 body: |
 508   bb.0:
 509     liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
 510
 511     ; CHECK-LABEL: name: insert_v_s256_v_s128_64
 512     ; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 513     ; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
 514     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3_sub4_sub5
 515     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 516     %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 517     %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
 518     %2:vgpr(s256) = G_INSERT %0, %1, 64
 519     S_ENDPGM 0, implicit %2
 520 ...
 521
 522 ---
 523
 524 name:            insert_v_s256_v_s128_96
 525 legalized:       true
 526 regBankSelected: true
 527
 528 body: |
 529   bb.0:
 530     liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
 531
 532     ; CHECK-LABEL: name: insert_v_s256_v_s128_96
 533     ; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 534     ; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
 535     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4_sub5_sub6
 536     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 537     %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 538     %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
 539     %2:vgpr(s256) = G_INSERT %0, %1, 96
 540     S_ENDPGM 0, implicit %2
 541 ...
 542
 543 ---
 544
 545 name:            insert_v_s256_v_s128_128
 546 legalized:       true
 547 regBankSelected: true
 548
 549 body: |
 550   bb.0:
 551     liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
 552
 553     ; CHECK-LABEL: name: insert_v_s256_v_s128_128
 554     ; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 555     ; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
 556     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5_sub6_sub7
 557     ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
 558     %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 559     %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
 560     %2:vgpr(s256) = G_INSERT %0, %1, 128
 561     S_ENDPGM 0, implicit %2
 562 ...