| blob | 66f8a2b111a5283d9876bf5dbfae53010015ce21 |
1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,FUNC %s
3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=R600,FUNC %s
5 ; BFI_INT Definition pattern from ISA docs
6 ; (y & x) | (z & ~x)
7 ;
8 ; FUNC-LABEL: {{^}}bfi_def:
9 ; R600: BFI_INT
11 ; GCN: v_bfi_b32
12 define amdgpu_kernel void @bfi_def(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
13 entry:
14 %0 = xor i32 %x, -1
15 %1 = and i32 %z, %0
16 %2 = and i32 %y, %x
17 %3 = or i32 %1, %2
18 store i32 %3, i32 addrspace(1)* %out
19 ret void
20 }
22 ; SHA-256 Ch function
23 ; z ^ (x & (y ^ z))
24 ; FUNC-LABEL: {{^}}bfi_sha256_ch:
25 ; R600: BFI_INT
27 ; GCN: v_bfi_b32
28 define amdgpu_kernel void @bfi_sha256_ch(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
29 entry:
30 %0 = xor i32 %y, %z
31 %1 = and i32 %x, %0
32 %2 = xor i32 %z, %1
33 store i32 %2, i32 addrspace(1)* %out
34 ret void
35 }
37 ; SHA-256 Ma function
38 ; ((x & z) | (y & (x | z)))
39 ; FUNC-LABEL: {{^}}bfi_sha256_ma:
40 ; R600: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W
41 ; R600: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W
43 ; GCN: v_xor_b32_e32 [[DST:v[0-9]+]], {{s[0-9]+, v[0-9]+}}
44 ; GCN: v_bfi_b32 {{v[0-9]+}}, [[DST]], {{s[0-9]+, v[0-9]+}}
45 define amdgpu_kernel void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
46 entry:
47 %0 = and i32 %x, %z
48 %1 = or i32 %x, %z
49 %2 = and i32 %y, %1
50 %3 = or i32 %0, %2
51 store i32 %3, i32 addrspace(1)* %out
52 ret void
53 }
55 ; FUNC-LABEL: {{^}}v_bitselect_v2i32_pat1:
56 ; GCN: s_waitcnt
57 ; GCN-NEXT: v_bfi_b32 v0, v2, v0, v4
58 ; GCN-NEXT: v_bfi_b32 v1, v3, v1, v5
59 ; GCN-NEXT: s_setpc_b64
60 define <2 x i32> @v_bitselect_v2i32_pat1(<2 x i32> %a, <2 x i32> %b, <2 x i32> %mask) {
61 %xor.0 = xor <2 x i32> %a, %mask
62 %and = and <2 x i32> %xor.0, %b
63 %bitselect = xor <2 x i32> %and, %mask
64 ret <2 x i32> %bitselect
65 }
67 ; FUNC-LABEL: {{^}}v_bitselect_i64_pat_0:
68 ; GCN: s_waitcnt
69 ; GCN-NEXT: v_bfi_b32 v1, v1, v3, v5
70 ; GCN-NEXT: v_bfi_b32 v0, v0, v2, v4
71 ; GCN-NEXT: s_setpc_b64
72 define i64 @v_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
73 %and0 = and i64 %a, %b
74 %not.a = xor i64 %a, -1
75 %and1 = and i64 %not.a, %mask
76 %bitselect = or i64 %and0, %and1
77 ret i64 %bitselect
78 }
80 ; FUNC-LABEL: {{^}}v_bitselect_i64_pat_1:
81 ; GCN: s_waitcnt
82 ; GCN-NEXT: v_bfi_b32 v1, v3, v1, v5
83 ; GCN-NEXT: v_bfi_b32 v0, v2, v0, v4
84 ; GCN-NEXT: s_setpc_b64
85 define i64 @v_bitselect_i64_pat_1(i64 %a, i64 %b, i64 %mask) {
86 %xor.0 = xor i64 %a, %mask
87 %and = and i64 %xor.0, %b
88 %bitselect = xor i64 %and, %mask
89 ret i64 %bitselect
90 }
92 ; FUNC-LABEL: {{^}}v_bitselect_i64_pat_2:
93 ; GCN: s_waitcnt
94 ; GCN-DAG: v_bfi_b32 v0, v2, v0, v4
95 ; GCN-DAG: v_bfi_b32 v1, v3, v1, v5
96 ; GCN-NEXT: s_setpc_b64
97 define i64 @v_bitselect_i64_pat_2(i64 %a, i64 %b, i64 %mask) {
98 %xor.0 = xor i64 %a, %mask
99 %and = and i64 %xor.0, %b
100 %bitselect = xor i64 %and, %mask
101 ret i64 %bitselect
102 }
104 ; FUNC-LABEL: {{^}}v_bfi_sha256_ma_i64:
105 ; GCN-DAG: v_xor_b32_e32 v1, v1, v3
106 ; GCN-DAG: v_xor_b32_e32 v0, v0, v2
107 ; GCN-DAG: v_bfi_b32 v1, v1, v5, v3
108 ; GCN-DAG: v_bfi_b32 v0, v0, v4, v2
109 define i64 @v_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {
110 entry:
111 %and0 = and i64 %x, %z
112 %or0 = or i64 %x, %z
113 %and1 = and i64 %y, %or0
114 %or1 = or i64 %and0, %and1
115 ret i64 %or1
116 }
118 ; FIXME: Should leave as 64-bit SALU ops
119 ; FUNC-LABEL: {{^}}s_bitselect_i64_pat_0:
120 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
121 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
122 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
123 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
124 ; GCN-DAG: v_bfi_b32
125 ; GCN-DAG: v_bfi_b32
126 define amdgpu_kernel void @s_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
127 %and0 = and i64 %a, %b
128 %not.a = xor i64 %a, -1
129 %and1 = and i64 %not.a, %mask
130 %bitselect = or i64 %and0, %and1
131 %scalar.use = add i64 %bitselect, 10
132 store i64 %scalar.use, i64 addrspace(1)* undef
133 ret void
134 }
136 ; FUNC-LABEL: {{^}}s_bitselect_i64_pat_1:
137 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
138 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
139 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
140 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
141 ; GCN-DAG: v_bfi_b32
142 ; GCN-DAG: v_bfi_b32
143 define amdgpu_kernel void @s_bitselect_i64_pat_1(i64 %a, i64 %b, i64 %mask) {
144 %xor.0 = xor i64 %a, %mask
145 %and = and i64 %xor.0, %b
146 %bitselect = xor i64 %and, %mask
148 %scalar.use = add i64 %bitselect, 10
149 store i64 %scalar.use, i64 addrspace(1)* undef
150 ret void
151 }
153 ; FUNC-LABEL: {{^}}s_bitselect_i64_pat_2:
154 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
155 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
156 ; GCN-DAG: v_bfi_b32
157 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
158 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
159 ; GCN-DAG: v_bfi_b32
160 define amdgpu_kernel void @s_bitselect_i64_pat_2(i64 %a, i64 %b, i64 %mask) {
161 %xor.0 = xor i64 %a, %mask
162 %and = and i64 %xor.0, %b
163 %bitselect = xor i64 %and, %mask
165 %scalar.use = add i64 %bitselect, 10
166 store i64 %scalar.use, i64 addrspace(1)* undef
167 ret void
168 }
170 ; FUNC-LABEL: {{^}}s_bfi_sha256_ma_i64:
171 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
172 ; GCN-DAG: v_xor_b32
173 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
174 ; GCN-DAG: v_xor_b32
175 ; GCN-DAG: v_bfi_b32
176 ; GCN: v_bfi_b32
177 define amdgpu_kernel void @s_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {
178 entry:
179 %and0 = and i64 %x, %z
180 %or0 = or i64 %x, %z
181 %and1 = and i64 %y, %or0
182 %or1 = or i64 %and0, %and1
184 %scalar.use = add i64 %or1, 10
185 store i64 %scalar.use, i64 addrspace(1)* undef
186 ret void
187 }