1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,SI
3 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,FLAT,TONGA
4 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,FLAT,VI
6 declare i32 @llvm.amdgcn.workitem.id.x() #1
8 declare i16 @llvm.bitreverse.i16(i16) #1
9 declare i32 @llvm.bitreverse.i32(i32) #1
10 declare i64 @llvm.bitreverse.i64(i64) #1
12 declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>) #1
13 declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) #1
15 declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1
16 declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1
18 define amdgpu_kernel void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 {
19 ; SI-LABEL: s_brev_i16:
21 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
22 ; SI-NEXT: s_load_dword s0, s[0:1], 0xb
23 ; SI-NEXT: s_mov_b32 s7, 0xf000
24 ; SI-NEXT: s_mov_b32 s6, -1
25 ; SI-NEXT: s_waitcnt lgkmcnt(0)
26 ; SI-NEXT: s_brev_b32 s0, s0
27 ; SI-NEXT: s_lshr_b32 s0, s0, 16
28 ; SI-NEXT: v_mov_b32_e32 v0, s0
29 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
32 ; FLAT-LABEL: s_brev_i16:
34 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
35 ; FLAT-NEXT: s_load_dword s0, s[0:1], 0x2c
36 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
37 ; FLAT-NEXT: s_mov_b32 s6, -1
38 ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
39 ; FLAT-NEXT: s_brev_b32 s0, s0
40 ; FLAT-NEXT: s_lshr_b32 s0, s0, 16
41 ; FLAT-NEXT: v_mov_b32_e32 v0, s0
42 ; FLAT-NEXT: buffer_store_short v0, off, s[4:7], 0
44 %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
45 store i16 %brev, i16 addrspace(1)* %out
49 define amdgpu_kernel void @v_brev_i16(i16 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %valptr) #0 {
50 ; SI-LABEL: v_brev_i16:
52 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
53 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
54 ; SI-NEXT: s_mov_b32 s7, 0xf000
55 ; SI-NEXT: s_mov_b32 s6, -1
56 ; SI-NEXT: s_mov_b32 s2, s6
57 ; SI-NEXT: s_mov_b32 s3, s7
58 ; SI-NEXT: s_waitcnt lgkmcnt(0)
59 ; SI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
60 ; SI-NEXT: s_waitcnt vmcnt(0)
61 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
62 ; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
63 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
66 ; FLAT-LABEL: v_brev_i16:
68 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
69 ; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
70 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
71 ; FLAT-NEXT: s_mov_b32 s6, -1
72 ; FLAT-NEXT: s_mov_b32 s2, s6
73 ; FLAT-NEXT: s_mov_b32 s3, s7
74 ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
75 ; FLAT-NEXT: buffer_load_ushort v0, off, s[0:3], 0
76 ; FLAT-NEXT: s_waitcnt vmcnt(0)
77 ; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
78 ; FLAT-NEXT: v_lshrrev_b32_e32 v0, 16, v0
79 ; FLAT-NEXT: buffer_store_short v0, off, s[4:7], 0
81 %val = load i16, i16 addrspace(1)* %valptr
82 %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
83 store i16 %brev, i16 addrspace(1)* %out
87 define amdgpu_kernel void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) #0 {
88 ; SI-LABEL: s_brev_i32:
90 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
91 ; SI-NEXT: s_load_dword s0, s[0:1], 0xb
92 ; SI-NEXT: s_mov_b32 s7, 0xf000
93 ; SI-NEXT: s_mov_b32 s6, -1
94 ; SI-NEXT: s_waitcnt lgkmcnt(0)
95 ; SI-NEXT: s_brev_b32 s0, s0
96 ; SI-NEXT: v_mov_b32_e32 v0, s0
97 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
100 ; FLAT-LABEL: s_brev_i32:
102 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
103 ; FLAT-NEXT: s_load_dword s0, s[0:1], 0x2c
104 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
105 ; FLAT-NEXT: s_mov_b32 s6, -1
106 ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
107 ; FLAT-NEXT: s_brev_b32 s0, s0
108 ; FLAT-NEXT: v_mov_b32_e32 v0, s0
109 ; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0
110 ; FLAT-NEXT: s_endpgm
111 %brev = call i32 @llvm.bitreverse.i32(i32 %val) #1
112 store i32 %brev, i32 addrspace(1)* %out
116 define amdgpu_kernel void @v_brev_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) #0 {
117 ; SI-LABEL: v_brev_i32:
119 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
120 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
121 ; SI-NEXT: s_mov_b32 s7, 0xf000
122 ; SI-NEXT: s_mov_b32 s2, 0
123 ; SI-NEXT: s_mov_b32 s3, s7
124 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
125 ; SI-NEXT: v_mov_b32_e32 v1, 0
126 ; SI-NEXT: s_waitcnt lgkmcnt(0)
127 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
128 ; SI-NEXT: s_mov_b32 s6, -1
129 ; SI-NEXT: s_waitcnt vmcnt(0)
130 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
131 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
134 ; FLAT-LABEL: v_brev_i32:
136 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
137 ; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
138 ; FLAT-NEXT: v_lshlrev_b32_e32 v0, 2, v0
139 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
140 ; FLAT-NEXT: s_mov_b32 s6, -1
141 ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
142 ; FLAT-NEXT: v_mov_b32_e32 v1, s1
143 ; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
144 ; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
145 ; FLAT-NEXT: flat_load_dword v0, v[0:1]
146 ; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
147 ; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
148 ; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0
149 ; FLAT-NEXT: s_endpgm
150 %tid = call i32 @llvm.amdgcn.workitem.id.x()
151 %gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
152 %val = load i32, i32 addrspace(1)* %gep
153 %brev = call i32 @llvm.bitreverse.i32(i32 %val) #1
154 store i32 %brev, i32 addrspace(1)* %out
158 define amdgpu_kernel void @s_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> %val) #0 {
159 ; SI-LABEL: s_brev_v2i32:
161 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
162 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
163 ; SI-NEXT: s_mov_b32 s7, 0xf000
164 ; SI-NEXT: s_mov_b32 s6, -1
165 ; SI-NEXT: s_waitcnt lgkmcnt(0)
166 ; SI-NEXT: s_brev_b32 s1, s1
167 ; SI-NEXT: s_brev_b32 s0, s0
168 ; SI-NEXT: v_mov_b32_e32 v0, s0
169 ; SI-NEXT: v_mov_b32_e32 v1, s1
170 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
173 ; FLAT-LABEL: s_brev_v2i32:
175 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
176 ; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
177 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
178 ; FLAT-NEXT: s_mov_b32 s6, -1
179 ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
180 ; FLAT-NEXT: s_brev_b32 s1, s1
181 ; FLAT-NEXT: s_brev_b32 s0, s0
182 ; FLAT-NEXT: v_mov_b32_e32 v0, s0
183 ; FLAT-NEXT: v_mov_b32_e32 v1, s1
184 ; FLAT-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
185 ; FLAT-NEXT: s_endpgm
186 %brev = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %val) #1
187 store <2 x i32> %brev, <2 x i32> addrspace(1)* %out
191 define amdgpu_kernel void @v_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) #0 {
192 ; SI-LABEL: v_brev_v2i32:
194 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
195 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
196 ; SI-NEXT: s_mov_b32 s7, 0xf000
197 ; SI-NEXT: s_mov_b32 s2, 0
198 ; SI-NEXT: s_mov_b32 s3, s7
199 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
200 ; SI-NEXT: v_mov_b32_e32 v1, 0
201 ; SI-NEXT: s_waitcnt lgkmcnt(0)
202 ; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64
203 ; SI-NEXT: s_mov_b32 s6, -1
204 ; SI-NEXT: s_waitcnt vmcnt(0)
205 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
206 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
207 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
210 ; FLAT-LABEL: v_brev_v2i32:
212 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
213 ; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
214 ; FLAT-NEXT: v_lshlrev_b32_e32 v0, 3, v0
215 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
216 ; FLAT-NEXT: s_mov_b32 s6, -1
217 ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
218 ; FLAT-NEXT: v_mov_b32_e32 v1, s1
219 ; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
220 ; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
221 ; FLAT-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
222 ; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
223 ; FLAT-NEXT: v_bfrev_b32_e32 v1, v1
224 ; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
225 ; FLAT-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
226 ; FLAT-NEXT: s_endpgm
227 %tid = call i32 @llvm.amdgcn.workitem.id.x()
228 %gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid
229 %val = load <2 x i32>, <2 x i32> addrspace(1)* %gep
230 %brev = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %val) #1
231 store <2 x i32> %brev, <2 x i32> addrspace(1)* %out
235 define amdgpu_kernel void @s_brev_i64(i64 addrspace(1)* noalias %out, i64 %val) #0 {
236 ; SI-LABEL: s_brev_i64:
238 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
239 ; SI-NEXT: s_mov_b32 s3, 0
240 ; SI-NEXT: s_mov_b32 s10, 0xff0000
241 ; SI-NEXT: s_mov_b32 s11, 0xff00
242 ; SI-NEXT: s_mov_b32 s7, s3
243 ; SI-NEXT: s_waitcnt lgkmcnt(0)
244 ; SI-NEXT: v_mov_b32_e32 v0, s4
245 ; SI-NEXT: v_alignbit_b32 v1, s5, v0, 24
246 ; SI-NEXT: v_alignbit_b32 v0, s5, v0, 8
247 ; SI-NEXT: s_lshr_b32 s6, s5, 8
248 ; SI-NEXT: v_and_b32_e32 v1, s10, v1
249 ; SI-NEXT: v_and_b32_e32 v0, 0xff000000, v0
250 ; SI-NEXT: s_lshr_b32 s2, s5, 24
251 ; SI-NEXT: s_and_b32 s6, s6, s11
252 ; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[2:3]
253 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
254 ; SI-NEXT: s_lshl_b64 s[8:9], s[4:5], 24
255 ; SI-NEXT: v_or_b32_e32 v0, s6, v0
256 ; SI-NEXT: v_mov_b32_e32 v1, s7
257 ; SI-NEXT: s_lshl_b64 s[6:7], s[4:5], 8
258 ; SI-NEXT: s_lshl_b32 s2, s4, 8
259 ; SI-NEXT: s_and_b32 s7, s7, 0xff
260 ; SI-NEXT: s_mov_b32 s6, s3
261 ; SI-NEXT: s_and_b32 s9, s9, s11
262 ; SI-NEXT: s_mov_b32 s8, s3
263 ; SI-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
264 ; SI-NEXT: s_lshl_b32 s9, s4, 24
265 ; SI-NEXT: s_and_b32 s5, s2, s10
266 ; SI-NEXT: s_mov_b32 s4, s3
267 ; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[4:5]
268 ; SI-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
269 ; SI-NEXT: v_or_b32_e32 v2, s2, v0
270 ; SI-NEXT: v_or_b32_e32 v3, s3, v1
271 ; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f
272 ; SI-NEXT: v_and_b32_e32 v1, s2, v3
273 ; SI-NEXT: v_and_b32_e32 v0, s2, v2
274 ; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f0
275 ; SI-NEXT: v_and_b32_e32 v3, s2, v3
276 ; SI-NEXT: v_and_b32_e32 v2, s2, v2
277 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
278 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
279 ; SI-NEXT: s_mov_b32 s2, 0x33333333
280 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
281 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
282 ; SI-NEXT: v_and_b32_e32 v1, s2, v3
283 ; SI-NEXT: v_and_b32_e32 v0, s2, v2
284 ; SI-NEXT: s_mov_b32 s2, 0xcccccccc
285 ; SI-NEXT: v_and_b32_e32 v3, s2, v3
286 ; SI-NEXT: v_and_b32_e32 v2, s2, v2
287 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
288 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
289 ; SI-NEXT: s_mov_b32 s2, 0x55555555
290 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
291 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
292 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
293 ; SI-NEXT: v_and_b32_e32 v1, s2, v3
294 ; SI-NEXT: v_and_b32_e32 v0, s2, v2
295 ; SI-NEXT: s_mov_b32 s2, 0xaaaaaaaa
296 ; SI-NEXT: v_and_b32_e32 v3, s2, v3
297 ; SI-NEXT: v_and_b32_e32 v2, s2, v2
298 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
299 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
300 ; SI-NEXT: s_mov_b32 s3, 0xf000
301 ; SI-NEXT: s_mov_b32 s2, -1
302 ; SI-NEXT: v_or_b32_e32 v0, v2, v0
303 ; SI-NEXT: v_or_b32_e32 v1, v3, v1
304 ; SI-NEXT: s_waitcnt lgkmcnt(0)
305 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
308 ; FLAT-LABEL: s_brev_i64:
310 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
311 ; FLAT-NEXT: s_mov_b32 s3, 0
312 ; FLAT-NEXT: s_mov_b32 s10, 0xff0000
313 ; FLAT-NEXT: s_mov_b32 s7, s3
314 ; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
315 ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
316 ; FLAT-NEXT: v_mov_b32_e32 v0, s4
317 ; FLAT-NEXT: v_alignbit_b32 v1, s5, v0, 24
318 ; FLAT-NEXT: v_alignbit_b32 v0, s5, v0, 8
319 ; FLAT-NEXT: s_bfe_u32 s6, s5, 0x80010
320 ; FLAT-NEXT: v_and_b32_e32 v1, s10, v1
321 ; FLAT-NEXT: v_and_b32_e32 v0, 0xff000000, v0
322 ; FLAT-NEXT: s_lshr_b32 s2, s5, 24
323 ; FLAT-NEXT: s_lshl_b32 s6, s6, 8
324 ; FLAT-NEXT: s_or_b64 s[6:7], s[6:7], s[2:3]
325 ; FLAT-NEXT: v_or_b32_e32 v0, v0, v1
326 ; FLAT-NEXT: s_lshl_b64 s[8:9], s[4:5], 24
327 ; FLAT-NEXT: v_or_b32_e32 v0, s6, v0
328 ; FLAT-NEXT: v_mov_b32_e32 v1, s7
329 ; FLAT-NEXT: s_lshl_b64 s[6:7], s[4:5], 8
330 ; FLAT-NEXT: s_lshl_b32 s2, s4, 8
331 ; FLAT-NEXT: s_and_b32 s7, s7, 0xff
332 ; FLAT-NEXT: s_mov_b32 s6, s3
333 ; FLAT-NEXT: s_and_b32 s9, s9, 0xff00
334 ; FLAT-NEXT: s_mov_b32 s8, s3
335 ; FLAT-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
336 ; FLAT-NEXT: s_lshl_b32 s9, s4, 24
337 ; FLAT-NEXT: s_and_b32 s5, s2, s10
338 ; FLAT-NEXT: s_mov_b32 s4, s3
339 ; FLAT-NEXT: s_or_b64 s[2:3], s[8:9], s[4:5]
340 ; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
341 ; FLAT-NEXT: v_or_b32_e32 v2, s2, v0
342 ; FLAT-NEXT: v_or_b32_e32 v3, s3, v1
343 ; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f
344 ; FLAT-NEXT: v_and_b32_e32 v1, s2, v3
345 ; FLAT-NEXT: v_and_b32_e32 v0, s2, v2
346 ; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f0
347 ; FLAT-NEXT: v_and_b32_e32 v3, s2, v3
348 ; FLAT-NEXT: v_and_b32_e32 v2, s2, v2
349 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
350 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
351 ; FLAT-NEXT: s_mov_b32 s2, 0x33333333
352 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
353 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
354 ; FLAT-NEXT: v_and_b32_e32 v1, s2, v3
355 ; FLAT-NEXT: v_and_b32_e32 v0, s2, v2
356 ; FLAT-NEXT: s_mov_b32 s2, 0xcccccccc
357 ; FLAT-NEXT: v_and_b32_e32 v3, s2, v3
358 ; FLAT-NEXT: v_and_b32_e32 v2, s2, v2
359 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
360 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
361 ; FLAT-NEXT: s_mov_b32 s2, 0x55555555
362 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
363 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
364 ; FLAT-NEXT: v_and_b32_e32 v1, s2, v3
365 ; FLAT-NEXT: v_and_b32_e32 v0, s2, v2
366 ; FLAT-NEXT: s_mov_b32 s2, 0xaaaaaaaa
367 ; FLAT-NEXT: v_and_b32_e32 v3, s2, v3
368 ; FLAT-NEXT: v_and_b32_e32 v2, s2, v2
369 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
370 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
371 ; FLAT-NEXT: s_mov_b32 s3, 0xf000
372 ; FLAT-NEXT: s_mov_b32 s2, -1
373 ; FLAT-NEXT: v_or_b32_e32 v0, v2, v0
374 ; FLAT-NEXT: v_or_b32_e32 v1, v3, v1
375 ; FLAT-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
376 ; FLAT-NEXT: s_endpgm
377 %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1
378 store i64 %brev, i64 addrspace(1)* %out
382 define amdgpu_kernel void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %valptr) #0 {
383 ; SI-LABEL: v_brev_i64:
385 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
386 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
387 ; SI-NEXT: s_mov_b32 s7, 0xf000
388 ; SI-NEXT: s_mov_b32 s2, 0
389 ; SI-NEXT: s_mov_b32 s3, s7
390 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
391 ; SI-NEXT: v_mov_b32_e32 v1, 0
392 ; SI-NEXT: s_waitcnt lgkmcnt(0)
393 ; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64
394 ; SI-NEXT: s_mov_b32 s0, 0xff00
395 ; SI-NEXT: s_mov_b32 s1, 0xf0f0f0f
396 ; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f0
397 ; SI-NEXT: s_mov_b32 s3, 0x33333333
398 ; SI-NEXT: s_mov_b32 s6, 0xcccccccc
399 ; SI-NEXT: s_mov_b32 s8, 0x55555555
400 ; SI-NEXT: s_mov_b32 s9, 0xaaaaaaaa
401 ; SI-NEXT: s_waitcnt vmcnt(0)
402 ; SI-NEXT: v_lshl_b64 v[2:3], v[0:1], 8
403 ; SI-NEXT: v_alignbit_b32 v4, v1, v0, 24
404 ; SI-NEXT: v_alignbit_b32 v5, v1, v0, 8
405 ; SI-NEXT: v_lshrrev_b32_e32 v7, 8, v1
406 ; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v1
407 ; SI-NEXT: v_lshl_b64 v[1:2], v[0:1], 24
408 ; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v0
409 ; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
410 ; SI-NEXT: v_and_b32_e32 v0, 0xff0000, v0
411 ; SI-NEXT: v_and_b32_e32 v4, 0xff0000, v4
412 ; SI-NEXT: v_and_b32_e32 v5, 0xff000000, v5
413 ; SI-NEXT: v_and_b32_e32 v7, s0, v7
414 ; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
415 ; SI-NEXT: v_and_b32_e32 v2, s0, v2
416 ; SI-NEXT: v_or_b32_e32 v4, v5, v4
417 ; SI-NEXT: v_or_b32_e32 v5, v7, v6
418 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
419 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
420 ; SI-NEXT: v_or_b32_e32 v1, v4, v5
421 ; SI-NEXT: v_or_b32_e32 v3, v0, v2
422 ; SI-NEXT: v_and_b32_e32 v0, s1, v1
423 ; SI-NEXT: v_and_b32_e32 v2, s2, v1
424 ; SI-NEXT: v_and_b32_e32 v1, s1, v3
425 ; SI-NEXT: v_and_b32_e32 v3, s2, v3
426 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
427 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
428 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
429 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
430 ; SI-NEXT: v_and_b32_e32 v1, s3, v3
431 ; SI-NEXT: v_and_b32_e32 v0, s3, v2
432 ; SI-NEXT: v_and_b32_e32 v3, s6, v3
433 ; SI-NEXT: v_and_b32_e32 v2, s6, v2
434 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
435 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
436 ; SI-NEXT: s_mov_b32 s6, -1
437 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
438 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
439 ; SI-NEXT: v_and_b32_e32 v1, s8, v3
440 ; SI-NEXT: v_and_b32_e32 v0, s8, v2
441 ; SI-NEXT: v_and_b32_e32 v3, s9, v3
442 ; SI-NEXT: v_and_b32_e32 v2, s9, v2
443 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
444 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
445 ; SI-NEXT: v_or_b32_e32 v1, v3, v1
446 ; SI-NEXT: v_or_b32_e32 v0, v2, v0
447 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
450 ; FLAT-LABEL: v_brev_i64:
452 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
453 ; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
454 ; FLAT-NEXT: v_lshlrev_b32_e32 v0, 3, v0
455 ; FLAT-NEXT: v_mov_b32_e32 v4, 8
456 ; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f
457 ; FLAT-NEXT: s_mov_b32 s3, 0xf0f0f0f0
458 ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
459 ; FLAT-NEXT: v_mov_b32_e32 v1, s1
460 ; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
461 ; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
462 ; FLAT-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
463 ; FLAT-NEXT: s_mov_b32 s0, 0x33333333
464 ; FLAT-NEXT: s_mov_b32 s1, 0xcccccccc
465 ; FLAT-NEXT: s_mov_b32 s6, 0x55555555
466 ; FLAT-NEXT: s_mov_b32 s8, 0xaaaaaaaa
467 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
468 ; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
469 ; FLAT-NEXT: v_lshlrev_b64 v[2:3], 24, v[0:1]
470 ; FLAT-NEXT: v_alignbit_b32 v2, v1, v0, 24
471 ; FLAT-NEXT: v_alignbit_b32 v6, v1, v0, 8
472 ; FLAT-NEXT: v_lshlrev_b32_sdwa v7, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
473 ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 8, v[0:1]
474 ; FLAT-NEXT: v_lshlrev_b32_e32 v4, 24, v0
475 ; FLAT-NEXT: v_lshlrev_b32_e32 v0, 8, v0
476 ; FLAT-NEXT: v_and_b32_e32 v2, 0xff0000, v2
477 ; FLAT-NEXT: v_and_b32_e32 v6, 0xff000000, v6
478 ; FLAT-NEXT: v_and_b32_e32 v0, 0xff0000, v0
479 ; FLAT-NEXT: v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
480 ; FLAT-NEXT: v_or_b32_e32 v2, v6, v2
481 ; FLAT-NEXT: v_and_b32_e32 v3, 0xff00, v3
482 ; FLAT-NEXT: v_or_b32_e32 v1, v2, v1
483 ; FLAT-NEXT: v_or_b32_e32 v0, v4, v0
484 ; FLAT-NEXT: v_or_b32_sdwa v2, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
485 ; FLAT-NEXT: v_or_b32_e32 v3, v0, v2
486 ; FLAT-NEXT: v_and_b32_e32 v0, s2, v1
487 ; FLAT-NEXT: v_and_b32_e32 v2, s3, v1
488 ; FLAT-NEXT: v_and_b32_e32 v1, s2, v3
489 ; FLAT-NEXT: v_and_b32_e32 v3, s3, v3
490 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
491 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
492 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
493 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
494 ; FLAT-NEXT: v_and_b32_e32 v1, s0, v3
495 ; FLAT-NEXT: v_and_b32_e32 v0, s0, v2
496 ; FLAT-NEXT: v_and_b32_e32 v3, s1, v3
497 ; FLAT-NEXT: v_and_b32_e32 v2, s1, v2
498 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
499 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
500 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
501 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
502 ; FLAT-NEXT: v_and_b32_e32 v1, s6, v3
503 ; FLAT-NEXT: v_and_b32_e32 v0, s6, v2
504 ; FLAT-NEXT: v_and_b32_e32 v3, s8, v3
505 ; FLAT-NEXT: v_and_b32_e32 v2, s8, v2
506 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
507 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
508 ; FLAT-NEXT: s_mov_b32 s6, -1
509 ; FLAT-NEXT: v_or_b32_e32 v1, v3, v1
510 ; FLAT-NEXT: v_or_b32_e32 v0, v2, v0
511 ; FLAT-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
512 ; FLAT-NEXT: s_endpgm
513 %tid = call i32 @llvm.amdgcn.workitem.id.x()
514 %gep = getelementptr i64, i64 addrspace(1)* %valptr, i32 %tid
515 %val = load i64, i64 addrspace(1)* %gep
516 %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1
517 store i64 %brev, i64 addrspace(1)* %out
521 define amdgpu_kernel void @s_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %val) #0 {
522 ; SI-LABEL: s_brev_v2i64:
524 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
525 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
526 ; SI-NEXT: s_mov_b32 s9, 0
527 ; SI-NEXT: s_mov_b32 s12, 0xff0000
528 ; SI-NEXT: s_mov_b32 s13, 0xff000000
529 ; SI-NEXT: s_mov_b32 s14, 0xff00
530 ; SI-NEXT: s_waitcnt lgkmcnt(0)
531 ; SI-NEXT: v_mov_b32_e32 v0, s2
532 ; SI-NEXT: v_alignbit_b32 v1, s3, v0, 24
533 ; SI-NEXT: v_alignbit_b32 v0, s3, v0, 8
534 ; SI-NEXT: s_lshr_b32 s6, s3, 8
535 ; SI-NEXT: v_and_b32_e32 v1, s12, v1
536 ; SI-NEXT: v_and_b32_e32 v0, s13, v0
537 ; SI-NEXT: s_lshr_b32 s8, s3, 24
538 ; SI-NEXT: s_and_b32 s6, s6, s14
539 ; SI-NEXT: s_mov_b32 s7, s9
540 ; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
541 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
542 ; SI-NEXT: s_lshl_b32 s8, s2, 8
543 ; SI-NEXT: v_or_b32_e32 v0, s6, v0
544 ; SI-NEXT: v_mov_b32_e32 v1, s7
545 ; SI-NEXT: s_and_b32 s11, s8, s12
546 ; SI-NEXT: s_lshl_b32 s7, s2, 24
547 ; SI-NEXT: s_mov_b32 s6, s9
548 ; SI-NEXT: s_mov_b32 s10, s9
549 ; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
550 ; SI-NEXT: s_lshl_b64 s[10:11], s[2:3], 8
551 ; SI-NEXT: s_lshl_b64 s[2:3], s[2:3], 24
552 ; SI-NEXT: s_movk_i32 s15, 0xff
553 ; SI-NEXT: s_and_b32 s11, s11, s15
554 ; SI-NEXT: s_mov_b32 s10, s9
555 ; SI-NEXT: s_and_b32 s3, s3, s14
556 ; SI-NEXT: s_mov_b32 s2, s9
557 ; SI-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
558 ; SI-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3]
559 ; SI-NEXT: v_mov_b32_e32 v4, s0
560 ; SI-NEXT: v_alignbit_b32 v5, s1, v4, 24
561 ; SI-NEXT: v_alignbit_b32 v4, s1, v4, 8
562 ; SI-NEXT: v_or_b32_e32 v2, s2, v0
563 ; SI-NEXT: s_lshr_b32 s2, s1, 8
564 ; SI-NEXT: v_or_b32_e32 v3, s3, v1
565 ; SI-NEXT: v_and_b32_e32 v5, s12, v5
566 ; SI-NEXT: v_and_b32_e32 v4, s13, v4
567 ; SI-NEXT: s_lshr_b32 s8, s1, 24
568 ; SI-NEXT: s_and_b32 s2, s2, s14
569 ; SI-NEXT: s_mov_b32 s3, s9
570 ; SI-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
571 ; SI-NEXT: v_or_b32_e32 v4, v4, v5
572 ; SI-NEXT: s_lshl_b32 s8, s0, 8
573 ; SI-NEXT: v_or_b32_e32 v4, s2, v4
574 ; SI-NEXT: v_mov_b32_e32 v5, s3
575 ; SI-NEXT: s_lshl_b32 s3, s0, 24
576 ; SI-NEXT: s_mov_b32 s2, s9
577 ; SI-NEXT: s_and_b32 s11, s8, s12
578 ; SI-NEXT: s_mov_b32 s16, 0xf0f0f0f
579 ; SI-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
580 ; SI-NEXT: s_lshl_b64 s[10:11], s[0:1], 8
581 ; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], 24
582 ; SI-NEXT: s_mov_b32 s17, 0xf0f0f0f0
583 ; SI-NEXT: v_and_b32_e32 v0, s16, v2
584 ; SI-NEXT: v_and_b32_e32 v1, s16, v3
585 ; SI-NEXT: v_and_b32_e32 v2, s17, v2
586 ; SI-NEXT: v_and_b32_e32 v3, s17, v3
587 ; SI-NEXT: s_and_b32 s11, s11, s15
588 ; SI-NEXT: s_mov_b32 s10, s9
589 ; SI-NEXT: s_and_b32 s1, s1, s14
590 ; SI-NEXT: s_mov_b32 s0, s9
591 ; SI-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
592 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
593 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
594 ; SI-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
595 ; SI-NEXT: v_or_b32_e32 v6, s0, v4
596 ; SI-NEXT: v_or_b32_e32 v7, s1, v5
597 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
598 ; SI-NEXT: s_mov_b32 s18, 0x33333333
599 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
600 ; SI-NEXT: s_mov_b32 s19, 0xcccccccc
601 ; SI-NEXT: v_and_b32_e32 v0, s18, v2
602 ; SI-NEXT: v_and_b32_e32 v1, s18, v3
603 ; SI-NEXT: v_and_b32_e32 v4, s16, v6
604 ; SI-NEXT: v_and_b32_e32 v5, s16, v7
605 ; SI-NEXT: v_and_b32_e32 v2, s19, v2
606 ; SI-NEXT: v_and_b32_e32 v3, s19, v3
607 ; SI-NEXT: v_and_b32_e32 v6, s17, v6
608 ; SI-NEXT: v_and_b32_e32 v7, s17, v7
609 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
610 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
611 ; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 4
612 ; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 4
613 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
614 ; SI-NEXT: v_or_b32_e32 v6, v6, v4
615 ; SI-NEXT: v_or_b32_e32 v7, v7, v5
616 ; SI-NEXT: s_mov_b32 s20, 0x55555555
617 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
618 ; SI-NEXT: s_mov_b32 s21, 0xaaaaaaaa
619 ; SI-NEXT: v_and_b32_e32 v0, s20, v2
620 ; SI-NEXT: v_and_b32_e32 v1, s20, v3
621 ; SI-NEXT: v_and_b32_e32 v4, s18, v6
622 ; SI-NEXT: v_and_b32_e32 v5, s18, v7
623 ; SI-NEXT: v_and_b32_e32 v2, s21, v2
624 ; SI-NEXT: v_and_b32_e32 v3, s21, v3
625 ; SI-NEXT: v_and_b32_e32 v6, s19, v6
626 ; SI-NEXT: v_and_b32_e32 v7, s19, v7
627 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
628 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
629 ; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 2
630 ; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 2
631 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
632 ; SI-NEXT: v_or_b32_e32 v0, v6, v4
633 ; SI-NEXT: v_or_b32_e32 v7, v7, v5
634 ; SI-NEXT: v_and_b32_e32 v5, s20, v7
635 ; SI-NEXT: v_and_b32_e32 v4, s20, v0
636 ; SI-NEXT: v_and_b32_e32 v6, s21, v0
637 ; SI-NEXT: v_and_b32_e32 v7, s21, v7
638 ; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
639 ; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 1
640 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
641 ; SI-NEXT: s_mov_b32 s7, 0xf000
642 ; SI-NEXT: s_mov_b32 s6, -1
643 ; SI-NEXT: v_or_b32_e32 v0, v6, v4
644 ; SI-NEXT: v_or_b32_e32 v1, v7, v5
645 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
648 ; FLAT-LABEL: s_brev_v2i64:
650 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
651 ; FLAT-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
652 ; FLAT-NEXT: s_mov_b32 s9, 0
653 ; FLAT-NEXT: s_mov_b32 s12, 0xff0000
654 ; FLAT-NEXT: s_mov_b32 s13, 0xff000000
655 ; FLAT-NEXT: s_mov_b32 s7, s9
656 ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
657 ; FLAT-NEXT: v_mov_b32_e32 v0, s2
658 ; FLAT-NEXT: v_alignbit_b32 v1, s3, v0, 24
659 ; FLAT-NEXT: v_alignbit_b32 v0, s3, v0, 8
660 ; FLAT-NEXT: s_bfe_u32 s6, s3, 0x80010
661 ; FLAT-NEXT: v_and_b32_e32 v1, s12, v1
662 ; FLAT-NEXT: v_and_b32_e32 v0, s13, v0
663 ; FLAT-NEXT: s_lshr_b32 s8, s3, 24
664 ; FLAT-NEXT: s_lshl_b32 s6, s6, 8
665 ; FLAT-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
666 ; FLAT-NEXT: v_or_b32_e32 v0, v0, v1
667 ; FLAT-NEXT: s_lshl_b32 s8, s2, 8
668 ; FLAT-NEXT: v_or_b32_e32 v0, s6, v0
669 ; FLAT-NEXT: v_mov_b32_e32 v1, s7
670 ; FLAT-NEXT: s_and_b32 s11, s8, s12
671 ; FLAT-NEXT: s_lshl_b32 s7, s2, 24
672 ; FLAT-NEXT: s_mov_b32 s6, s9
673 ; FLAT-NEXT: s_mov_b32 s10, s9
674 ; FLAT-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
675 ; FLAT-NEXT: s_lshl_b64 s[10:11], s[2:3], 8
676 ; FLAT-NEXT: s_movk_i32 s14, 0xff
677 ; FLAT-NEXT: s_lshl_b64 s[2:3], s[2:3], 24
678 ; FLAT-NEXT: s_mov_b32 s15, 0xff00
679 ; FLAT-NEXT: s_and_b32 s11, s11, s14
680 ; FLAT-NEXT: s_mov_b32 s10, s9
681 ; FLAT-NEXT: s_and_b32 s3, s3, s15
682 ; FLAT-NEXT: s_mov_b32 s2, s9
683 ; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
684 ; FLAT-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3]
685 ; FLAT-NEXT: v_mov_b32_e32 v4, s0
686 ; FLAT-NEXT: v_alignbit_b32 v5, s1, v4, 24
687 ; FLAT-NEXT: v_alignbit_b32 v4, s1, v4, 8
688 ; FLAT-NEXT: v_or_b32_e32 v2, s2, v0
689 ; FLAT-NEXT: s_bfe_u32 s2, s1, 0x80010
690 ; FLAT-NEXT: v_or_b32_e32 v3, s3, v1
691 ; FLAT-NEXT: v_and_b32_e32 v5, s12, v5
692 ; FLAT-NEXT: v_and_b32_e32 v4, s13, v4
693 ; FLAT-NEXT: s_lshr_b32 s8, s1, 24
694 ; FLAT-NEXT: s_lshl_b32 s2, s2, 8
695 ; FLAT-NEXT: s_mov_b32 s3, s9
696 ; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
697 ; FLAT-NEXT: v_or_b32_e32 v4, v4, v5
698 ; FLAT-NEXT: s_lshl_b32 s8, s0, 8
699 ; FLAT-NEXT: v_or_b32_e32 v4, s2, v4
700 ; FLAT-NEXT: v_mov_b32_e32 v5, s3
701 ; FLAT-NEXT: s_lshl_b32 s3, s0, 24
702 ; FLAT-NEXT: s_mov_b32 s2, s9
703 ; FLAT-NEXT: s_and_b32 s11, s8, s12
704 ; FLAT-NEXT: s_mov_b32 s16, 0xf0f0f0f
705 ; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
706 ; FLAT-NEXT: s_lshl_b64 s[10:11], s[0:1], 8
707 ; FLAT-NEXT: s_lshl_b64 s[0:1], s[0:1], 24
708 ; FLAT-NEXT: s_mov_b32 s17, 0xf0f0f0f0
709 ; FLAT-NEXT: v_and_b32_e32 v0, s16, v2
710 ; FLAT-NEXT: v_and_b32_e32 v1, s16, v3
711 ; FLAT-NEXT: v_and_b32_e32 v2, s17, v2
712 ; FLAT-NEXT: v_and_b32_e32 v3, s17, v3
713 ; FLAT-NEXT: s_and_b32 s11, s11, s14
714 ; FLAT-NEXT: s_mov_b32 s10, s9
715 ; FLAT-NEXT: s_and_b32 s1, s1, s15
716 ; FLAT-NEXT: s_mov_b32 s0, s9
717 ; FLAT-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
718 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
719 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
720 ; FLAT-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
721 ; FLAT-NEXT: v_or_b32_e32 v6, s0, v4
722 ; FLAT-NEXT: v_or_b32_e32 v7, s1, v5
723 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
724 ; FLAT-NEXT: s_mov_b32 s18, 0x33333333
725 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
726 ; FLAT-NEXT: s_mov_b32 s19, 0xcccccccc
727 ; FLAT-NEXT: v_and_b32_e32 v0, s18, v2
728 ; FLAT-NEXT: v_and_b32_e32 v1, s18, v3
729 ; FLAT-NEXT: v_and_b32_e32 v4, s16, v6
730 ; FLAT-NEXT: v_and_b32_e32 v5, s16, v7
731 ; FLAT-NEXT: v_and_b32_e32 v2, s19, v2
732 ; FLAT-NEXT: v_and_b32_e32 v3, s19, v3
733 ; FLAT-NEXT: v_and_b32_e32 v6, s17, v6
734 ; FLAT-NEXT: v_and_b32_e32 v7, s17, v7
735 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
736 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
737 ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 4, v[4:5]
738 ; FLAT-NEXT: v_lshrrev_b64 v[6:7], 4, v[6:7]
739 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
740 ; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
741 ; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
742 ; FLAT-NEXT: s_mov_b32 s20, 0x55555555
743 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
744 ; FLAT-NEXT: s_mov_b32 s21, 0xaaaaaaaa
745 ; FLAT-NEXT: v_and_b32_e32 v0, s20, v2
746 ; FLAT-NEXT: v_and_b32_e32 v1, s20, v3
747 ; FLAT-NEXT: v_and_b32_e32 v4, s18, v6
748 ; FLAT-NEXT: v_and_b32_e32 v5, s18, v7
749 ; FLAT-NEXT: v_and_b32_e32 v2, s21, v2
750 ; FLAT-NEXT: v_and_b32_e32 v3, s21, v3
751 ; FLAT-NEXT: v_and_b32_e32 v6, s19, v6
752 ; FLAT-NEXT: v_and_b32_e32 v7, s19, v7
753 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
754 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
755 ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 2, v[4:5]
756 ; FLAT-NEXT: v_lshrrev_b64 v[6:7], 2, v[6:7]
757 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
758 ; FLAT-NEXT: v_or_b32_e32 v0, v6, v4
759 ; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
760 ; FLAT-NEXT: v_and_b32_e32 v5, s20, v7
761 ; FLAT-NEXT: v_and_b32_e32 v4, s20, v0
762 ; FLAT-NEXT: v_and_b32_e32 v6, s21, v0
763 ; FLAT-NEXT: v_and_b32_e32 v7, s21, v7
764 ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
765 ; FLAT-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
766 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
767 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
768 ; FLAT-NEXT: s_mov_b32 s6, -1
769 ; FLAT-NEXT: v_or_b32_e32 v0, v6, v4
770 ; FLAT-NEXT: v_or_b32_e32 v1, v7, v5
771 ; FLAT-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
772 ; FLAT-NEXT: s_endpgm
773 %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
774 store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
778 define amdgpu_kernel void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %valptr) #0 {
779 ; SI-LABEL: v_brev_v2i64:
781 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
782 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
783 ; SI-NEXT: s_mov_b32 s7, 0xf000
784 ; SI-NEXT: s_mov_b32 s2, 0
785 ; SI-NEXT: s_mov_b32 s3, s7
786 ; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
787 ; SI-NEXT: v_mov_b32_e32 v1, 0
788 ; SI-NEXT: s_waitcnt lgkmcnt(0)
789 ; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr64
790 ; SI-NEXT: s_mov_b32 s0, 0xff00
791 ; SI-NEXT: s_mov_b32 s1, 0xf0f0f0f
792 ; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f0
793 ; SI-NEXT: s_mov_b32 s3, 0x33333333
794 ; SI-NEXT: s_mov_b32 s8, 0xcccccccc
795 ; SI-NEXT: s_mov_b32 s9, 0x55555555
796 ; SI-NEXT: s_mov_b32 s10, 0xaaaaaaaa
797 ; SI-NEXT: s_mov_b32 s6, -1
798 ; SI-NEXT: s_waitcnt vmcnt(0)
799 ; SI-NEXT: v_lshl_b64 v[4:5], v[2:3], 8
800 ; SI-NEXT: v_alignbit_b32 v6, v3, v2, 24
801 ; SI-NEXT: v_alignbit_b32 v7, v3, v2, 8
802 ; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v3
803 ; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v3
804 ; SI-NEXT: v_lshl_b64 v[3:4], v[2:3], 24
805 ; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v2
806 ; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v2
807 ; SI-NEXT: v_lshl_b64 v[2:3], v[0:1], 8
808 ; SI-NEXT: v_alignbit_b32 v12, v1, v0, 24
809 ; SI-NEXT: v_alignbit_b32 v13, v1, v0, 8
810 ; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v1
811 ; SI-NEXT: v_lshrrev_b32_e32 v15, 8, v1
812 ; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v0
813 ; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v0
814 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 24
815 ; SI-NEXT: v_and_b32_e32 v6, 0xff0000, v6
816 ; SI-NEXT: v_and_b32_e32 v7, 0xff000000, v7
817 ; SI-NEXT: v_mov_b32_e32 v0, 0xff0000
818 ; SI-NEXT: v_or_b32_e32 v6, v7, v6
819 ; SI-NEXT: v_mov_b32_e32 v7, 0xff00
820 ; SI-NEXT: v_and_b32_e32 v2, v0, v11
821 ; SI-NEXT: v_and_b32_e32 v11, v0, v12
822 ; SI-NEXT: v_and_b32_e32 v9, s0, v9
823 ; SI-NEXT: v_and_b32_e32 v12, 0xff000000, v13
824 ; SI-NEXT: v_and_b32_e32 v0, v0, v17
825 ; SI-NEXT: v_and_b32_e32 v13, v7, v15
826 ; SI-NEXT: v_and_b32_e32 v1, v7, v1
827 ; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
828 ; SI-NEXT: v_or_b32_e32 v8, v9, v8
829 ; SI-NEXT: v_or_b32_e32 v2, v10, v2
830 ; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
831 ; SI-NEXT: v_and_b32_e32 v4, s0, v4
832 ; SI-NEXT: v_or_b32_e32 v7, v16, v0
833 ; SI-NEXT: v_or_b32_e32 v1, v1, v3
834 ; SI-NEXT: v_or_b32_e32 v9, v12, v11
835 ; SI-NEXT: v_or_b32_e32 v10, v13, v14
836 ; SI-NEXT: v_or_b32_e32 v0, v4, v5
837 ; SI-NEXT: v_or_b32_e32 v5, v9, v10
838 ; SI-NEXT: v_or_b32_e32 v6, v6, v8
839 ; SI-NEXT: v_or_b32_e32 v7, v7, v1
840 ; SI-NEXT: v_or_b32_e32 v3, v2, v0
841 ; SI-NEXT: v_and_b32_e32 v0, s1, v6
842 ; SI-NEXT: v_and_b32_e32 v2, s2, v6
843 ; SI-NEXT: v_and_b32_e32 v4, s1, v5
844 ; SI-NEXT: v_and_b32_e32 v6, s2, v5
845 ; SI-NEXT: v_and_b32_e32 v5, s1, v7
846 ; SI-NEXT: v_and_b32_e32 v7, s2, v7
847 ; SI-NEXT: v_and_b32_e32 v1, s1, v3
848 ; SI-NEXT: v_and_b32_e32 v3, s2, v3
849 ; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 4
850 ; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 4
851 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
852 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
853 ; SI-NEXT: v_or_b32_e32 v7, v7, v5
854 ; SI-NEXT: v_or_b32_e32 v6, v6, v4
855 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
856 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
857 ; SI-NEXT: v_and_b32_e32 v5, s3, v7
858 ; SI-NEXT: v_and_b32_e32 v4, s3, v6
859 ; SI-NEXT: v_and_b32_e32 v7, s8, v7
860 ; SI-NEXT: v_and_b32_e32 v6, s8, v6
861 ; SI-NEXT: v_and_b32_e32 v1, s3, v3
862 ; SI-NEXT: v_and_b32_e32 v0, s3, v2
863 ; SI-NEXT: v_and_b32_e32 v3, s8, v3
864 ; SI-NEXT: v_and_b32_e32 v2, s8, v2
865 ; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 2
866 ; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 2
867 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
868 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
869 ; SI-NEXT: v_or_b32_e32 v7, v7, v5
870 ; SI-NEXT: v_or_b32_e32 v9, v6, v4
871 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
872 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
873 ; SI-NEXT: v_and_b32_e32 v5, s9, v7
874 ; SI-NEXT: v_and_b32_e32 v4, s9, v9
875 ; SI-NEXT: v_and_b32_e32 v1, s9, v3
876 ; SI-NEXT: v_and_b32_e32 v0, s9, v2
877 ; SI-NEXT: v_and_b32_e32 v6, s10, v7
878 ; SI-NEXT: v_lshl_b64 v[7:8], v[4:5], 1
879 ; SI-NEXT: v_and_b32_e32 v5, s10, v9
880 ; SI-NEXT: v_and_b32_e32 v3, s10, v3
881 ; SI-NEXT: v_and_b32_e32 v2, s10, v2
882 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
883 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
884 ; SI-NEXT: v_lshr_b64 v[4:5], v[5:6], 1
885 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
886 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
887 ; SI-NEXT: v_or_b32_e32 v1, v5, v8
888 ; SI-NEXT: v_or_b32_e32 v0, v4, v7
889 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
892 ; FLAT-LABEL: v_brev_v2i64:
894 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
895 ; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
896 ; FLAT-NEXT: v_lshlrev_b32_e32 v0, 4, v0
897 ; FLAT-NEXT: v_mov_b32_e32 v8, 8
898 ; FLAT-NEXT: v_mov_b32_e32 v10, 0xff0000
899 ; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f
900 ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
901 ; FLAT-NEXT: v_mov_b32_e32 v1, s1
902 ; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
903 ; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
904 ; FLAT-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
905 ; FLAT-NEXT: s_mov_b32 s0, 0xf0f0f0f0
906 ; FLAT-NEXT: s_mov_b32 s1, 0x33333333
907 ; FLAT-NEXT: s_mov_b32 s3, 0xcccccccc
908 ; FLAT-NEXT: s_mov_b32 s8, 0x55555555
909 ; FLAT-NEXT: s_mov_b32 s9, 0xaaaaaaaa
910 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
911 ; FLAT-NEXT: s_mov_b32 s6, -1
912 ; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
913 ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 24, v[2:3]
914 ; FLAT-NEXT: v_lshlrev_b32_sdwa v12, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
915 ; FLAT-NEXT: v_lshlrev_b32_sdwa v15, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
916 ; FLAT-NEXT: v_lshlrev_b64 v[8:9], 8, v[0:1]
917 ; FLAT-NEXT: v_lshlrev_b64 v[6:7], 8, v[2:3]
918 ; FLAT-NEXT: v_alignbit_b32 v4, v3, v2, 24
919 ; FLAT-NEXT: v_alignbit_b32 v11, v3, v2, 8
920 ; FLAT-NEXT: v_or_b32_sdwa v3, v12, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
921 ; FLAT-NEXT: v_or_b32_sdwa v12, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
922 ; FLAT-NEXT: v_alignbit_b32 v13, v1, v0, 24
923 ; FLAT-NEXT: v_alignbit_b32 v14, v1, v0, 8
924 ; FLAT-NEXT: v_lshlrev_b32_e32 v8, 24, v0
925 ; FLAT-NEXT: v_lshlrev_b32_e32 v15, 8, v0
926 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 24, v[0:1]
927 ; FLAT-NEXT: v_lshlrev_b32_e32 v6, 24, v2
928 ; FLAT-NEXT: v_lshlrev_b32_e32 v2, 8, v2
929 ; FLAT-NEXT: v_and_b32_e32 v0, 0xff0000, v4
930 ; FLAT-NEXT: v_and_b32_e32 v4, 0xff000000, v11
931 ; FLAT-NEXT: v_and_b32_e32 v2, v10, v2
932 ; FLAT-NEXT: v_and_b32_e32 v11, v10, v13
933 ; FLAT-NEXT: v_or_b32_e32 v0, v4, v0
934 ; FLAT-NEXT: v_and_b32_e32 v1, 0xff00, v1
935 ; FLAT-NEXT: v_and_b32_e32 v13, 0xff000000, v14
936 ; FLAT-NEXT: v_and_b32_e32 v4, 0xff00, v5
937 ; FLAT-NEXT: v_and_b32_e32 v10, v10, v15
938 ; FLAT-NEXT: v_or_b32_e32 v5, v13, v11
939 ; FLAT-NEXT: v_or_b32_e32 v2, v6, v2
940 ; FLAT-NEXT: v_or_b32_e32 v3, v0, v3
941 ; FLAT-NEXT: v_or_b32_sdwa v0, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
942 ; FLAT-NEXT: v_or_b32_e32 v6, v8, v10
943 ; FLAT-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
944 ; FLAT-NEXT: v_or_b32_e32 v7, v2, v0
945 ; FLAT-NEXT: v_or_b32_e32 v5, v5, v12
946 ; FLAT-NEXT: v_or_b32_e32 v8, v6, v1
947 ; FLAT-NEXT: v_and_b32_e32 v0, s2, v3
948 ; FLAT-NEXT: v_and_b32_e32 v1, s2, v7
949 ; FLAT-NEXT: v_and_b32_e32 v2, s0, v3
950 ; FLAT-NEXT: v_and_b32_e32 v3, s0, v7
951 ; FLAT-NEXT: v_and_b32_e32 v4, s2, v5
952 ; FLAT-NEXT: v_and_b32_e32 v6, s0, v5
953 ; FLAT-NEXT: v_and_b32_e32 v5, s2, v8
954 ; FLAT-NEXT: v_and_b32_e32 v7, s0, v8
955 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
956 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
957 ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 4, v[4:5]
958 ; FLAT-NEXT: v_lshrrev_b64 v[6:7], 4, v[6:7]
959 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
960 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
961 ; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
962 ; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
963 ; FLAT-NEXT: v_and_b32_e32 v1, s1, v3
964 ; FLAT-NEXT: v_and_b32_e32 v0, s1, v2
965 ; FLAT-NEXT: v_and_b32_e32 v5, s1, v7
966 ; FLAT-NEXT: v_and_b32_e32 v4, s1, v6
967 ; FLAT-NEXT: v_and_b32_e32 v3, s3, v3
968 ; FLAT-NEXT: v_and_b32_e32 v2, s3, v2
969 ; FLAT-NEXT: v_and_b32_e32 v7, s3, v7
970 ; FLAT-NEXT: v_and_b32_e32 v6, s3, v6
971 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
972 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
973 ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 2, v[4:5]
974 ; FLAT-NEXT: v_lshrrev_b64 v[6:7], 2, v[6:7]
975 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
976 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
977 ; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
978 ; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
979 ; FLAT-NEXT: v_and_b32_e32 v1, s8, v3
980 ; FLAT-NEXT: v_and_b32_e32 v0, s8, v2
981 ; FLAT-NEXT: v_and_b32_e32 v5, s8, v7
982 ; FLAT-NEXT: v_and_b32_e32 v4, s8, v6
983 ; FLAT-NEXT: v_and_b32_e32 v3, s9, v3
984 ; FLAT-NEXT: v_and_b32_e32 v2, s9, v2
985 ; FLAT-NEXT: v_and_b32_e32 v7, s9, v7
986 ; FLAT-NEXT: v_and_b32_e32 v6, s9, v6
987 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
988 ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
989 ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
990 ; FLAT-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
991 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
992 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
993 ; FLAT-NEXT: v_or_b32_e32 v1, v7, v5
994 ; FLAT-NEXT: v_or_b32_e32 v0, v6, v4
995 ; FLAT-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
996 ; FLAT-NEXT: s_endpgm
997 %tid = call i32 @llvm.amdgcn.workitem.id.x()
998 %gep = getelementptr <2 x i64> , <2 x i64> addrspace(1)* %valptr, i32 %tid
999 %val = load <2 x i64>, <2 x i64> addrspace(1)* %gep
1000 %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
1001 store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
1005 define float @missing_truncate_promote_bitreverse(i32 %arg) {
1006 ; SI-LABEL: missing_truncate_promote_bitreverse:
1007 ; SI: ; %bb.0: ; %bb
1008 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1009 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
1010 ; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
1011 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
1012 ; SI-NEXT: s_setpc_b64 s[30:31]
1014 ; FLAT-LABEL: missing_truncate_promote_bitreverse:
1015 ; FLAT: ; %bb.0: ; %bb
1016 ; FLAT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1017 ; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
1018 ; FLAT-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
1019 ; FLAT-NEXT: s_setpc_b64 s[30:31]
1021 %tmp = trunc i32 %arg to i16
1022 %tmp1 = call i16 @llvm.bitreverse.i16(i16 %tmp)
1023 %tmp2 = bitcast i16 %tmp1 to half
1024 %tmp3 = fpext half %tmp2 to float
1028 attributes #0 = { nounwind }
1029 attributes #1 = { nounwind readnone }