1 # RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
2 # Check that %11 and %20 have been coalesced.
3 # CHECK: IMAGE_SAMPLE_C_D_O_V1_V16 %[[REG:[0-9]+]]
4 # CHECK: IMAGE_SAMPLE_C_D_O_V1_V16 %[[REG]]
9 tracksRegLiveness: true
11 - { id: 0, class: sreg_64 }
12 - { id: 1, class: vgpr_32 }
13 - { id: 2, class: vgpr_32 }
14 - { id: 3, class: sreg_256 }
15 - { id: 4, class: sgpr_128 }
16 - { id: 5, class: sreg_256 }
17 - { id: 6, class: sgpr_128 }
18 - { id: 7, class: sreg_512 }
19 - { id: 9, class: vreg_512 }
20 - { id: 11, class: vreg_512 }
21 - { id: 18, class: vgpr_32 }
22 - { id: 20, class: vreg_512 }
23 - { id: 27, class: vgpr_32 }
25 - { reg: '$sgpr2_sgpr3', virtual-reg: '%0' }
26 - { reg: '$vgpr2', virtual-reg: '%1' }
27 - { reg: '$vgpr3', virtual-reg: '%2' }
29 isFrameAddressTaken: false
30 isReturnAddressTaken: false
39 hasOpaqueSPAdjustment: false
41 hasMustTailInVarArgFunc: false
44 liveins: $sgpr2_sgpr3, $vgpr2, $vgpr3
46 %0 = COPY $sgpr2_sgpr3
49 %3 = S_LOAD_DWORDX8_IMM %0, 0, 0, 0
50 %4 = S_LOAD_DWORDX4_IMM %0, 12, 0, 0
51 %5 = S_LOAD_DWORDX8_IMM %0, 16, 0, 0
52 %6 = S_LOAD_DWORDX4_IMM %0, 28, 0, 0
53 undef %7.sub0 = S_MOV_B32 212739
64 dead %18 = IMAGE_SAMPLE_C_D_O_V1_V16 %11, %3, %4, 1, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec
73 dead %27 = IMAGE_SAMPLE_C_D_O_V1_V16 %20, %5, %6, 1, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec