1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,ALL %s
2 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-opt-exec-mask-pre-ra=0 < %s | FileCheck -enable-var-scope -check-prefixes=DISABLED,ALL %s
4 ; ALL-LABEL: {{^}}simple_nested_if:
5 ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
6 ; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9_]+]]
7 ; GCN-NEXT: s_cbranch_execz [[ENDIF]]
8 ; GCN: s_and_b64 exec, exec, vcc
9 ; GCN-NEXT: ; mask branch [[ENDIF]]
10 ; GCN-NEXT: s_cbranch_execz [[ENDIF]]
11 ; GCN-NEXT: {{^BB[0-9_]+}}:
13 ; GCN-NEXT: {{^}}[[ENDIF]]:
14 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
19 ; DISABLED: s_or_b64 exec, exec
20 ; DISABLED: s_or_b64 exec, exec
21 define amdgpu_kernel void @simple_nested_if(i32 addrspace(1)* nocapture %arg) {
23 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
24 %tmp1 = icmp ugt i32 %tmp, 1
25 br i1 %tmp1, label %bb.outer.then, label %bb.outer.end
27 bb.outer.then: ; preds = %bb
28 %tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
29 store i32 0, i32 addrspace(1)* %tmp4, align 4
30 %tmp5 = icmp eq i32 %tmp, 2
31 br i1 %tmp5, label %bb.outer.end, label %bb.inner.then
33 bb.inner.then: ; preds = %bb.outer.then
34 %tmp7 = add i32 %tmp, 1
35 %tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
36 store i32 1, i32 addrspace(1)* %tmp9, align 4
37 br label %bb.outer.end
39 bb.outer.end: ; preds = %bb.outer.then, %bb.inner.then, %bb
40 store i32 3, i32 addrspace(3)* null
44 ; ALL-LABEL: {{^}}uncollapsable_nested_if:
45 ; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
46 ; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
47 ; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
48 ; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
49 ; GCN-NEXT: ; mask branch [[ENDIF_INNER:BB[0-9_]+]]
50 ; GCN-NEXT: s_cbranch_execz [[ENDIF_INNER]]
51 ; GCN-NEXT: {{^BB[0-9_]+}}:
53 ; GCN-NEXT: {{^}}[[ENDIF_INNER]]:
54 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER]]
56 ; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
57 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
60 define amdgpu_kernel void @uncollapsable_nested_if(i32 addrspace(1)* nocapture %arg) {
62 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
63 %tmp1 = icmp ugt i32 %tmp, 1
64 br i1 %tmp1, label %bb.outer.then, label %bb.outer.end
66 bb.outer.then: ; preds = %bb
67 %tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
68 store i32 0, i32 addrspace(1)* %tmp4, align 4
69 %tmp5 = icmp eq i32 %tmp, 2
70 br i1 %tmp5, label %bb.inner.end, label %bb.inner.then
72 bb.inner.then: ; preds = %bb.outer.then
73 %tmp7 = add i32 %tmp, 1
74 %tmp8 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
75 store i32 1, i32 addrspace(1)* %tmp8, align 4
76 br label %bb.inner.end
78 bb.inner.end: ; preds = %bb.inner.then, %bb.outer.then
79 %tmp9 = add i32 %tmp, 2
80 %tmp10 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp9
81 store i32 2, i32 addrspace(1)* %tmp10, align 4
82 br label %bb.outer.end
84 bb.outer.end: ; preds = %bb.inner.then, %bb
85 store i32 3, i32 addrspace(3)* null
89 ; ALL-LABEL: {{^}}nested_if_if_else:
90 ; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
91 ; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
92 ; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
93 ; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
94 ; GCN-NEXT: s_xor_b64 [[SAVEEXEC_INNER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_INNER]]
95 ; GCN-NEXT: ; mask branch [[THEN_INNER:BB[0-9_]+]]
96 ; GCN-NEXT: s_cbranch_execz [[THEN_INNER]]
97 ; GCN-NEXT: {{^BB[0-9_]+}}:
99 ; GCN-NEXT: {{^}}[[THEN_INNER]]:
100 ; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_INNER3:s\[[0-9:]+\]]], [[SAVEEXEC_INNER2]]
101 ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_INNER3]]
102 ; GCN-NEXT: ; mask branch [[ENDIF_OUTER]]
104 ; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
105 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
108 define amdgpu_kernel void @nested_if_if_else(i32 addrspace(1)* nocapture %arg) {
110 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
111 %tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
112 store i32 0, i32 addrspace(1)* %tmp1, align 4
113 %tmp2 = icmp ugt i32 %tmp, 1
114 br i1 %tmp2, label %bb.outer.then, label %bb.outer.end
116 bb.outer.then: ; preds = %bb
117 %tmp5 = icmp eq i32 %tmp, 2
118 br i1 %tmp5, label %bb.then, label %bb.else
120 bb.then: ; preds = %bb.outer.then
121 %tmp3 = add i32 %tmp, 1
122 %tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp3
123 store i32 1, i32 addrspace(1)* %tmp4, align 4
124 br label %bb.outer.end
126 bb.else: ; preds = %bb.outer.then
127 %tmp7 = add i32 %tmp, 2
128 %tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
129 store i32 2, i32 addrspace(1)* %tmp9, align 4
130 br label %bb.outer.end
132 bb.outer.end: ; preds = %bb, %bb.then, %bb.else
133 store i32 3, i32 addrspace(3)* null
137 ; ALL-LABEL: {{^}}nested_if_else_if:
138 ; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
139 ; GCN-NEXT: s_xor_b64 [[SAVEEXEC_OUTER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_OUTER]]
140 ; GCN-NEXT: ; mask branch [[THEN_OUTER:BB[0-9_]+]]
141 ; GCN-NEXT: s_cbranch_execz [[THEN_OUTER]]
142 ; GCN-NEXT: {{^BB[0-9_]+}}:
144 ; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_ELSE:s\[[0-9:]+\]]]
145 ; GCN-NEXT: ; mask branch [[THEN_OUTER_FLOW:BB[0-9_]+]]
146 ; GCN-NEXT: s_cbranch_execz [[THEN_OUTER_FLOW]]
147 ; GCN-NEXT: {{^BB[0-9_]+}}:
149 ; GCN-NEXT: {{^}}[[THEN_OUTER_FLOW]]:
150 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_ELSE]]
151 ; GCN-NEXT: {{^}}[[THEN_OUTER]]:
152 ; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_OUTER3:s\[[0-9:]+\]]], [[SAVEEXEC_OUTER2]]
153 ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_OUTER3]]
154 ; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
155 ; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
156 ; GCN-NEXT: {{^BB[0-9_]+}}:
158 ; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_THEN:s\[[0-9:]+\]]]
159 ; GCN-NEXT: ; mask branch [[FLOW1:BB[0-9_]+]]
160 ; GCN-NEXT: s_cbranch_execz [[FLOW1]]
161 ; GCN-NEXT: {{^BB[0-9_]+}}:
163 ; GCN-NEXT: [[FLOW1]]:
164 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_THEN]]
165 ; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
166 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
169 define amdgpu_kernel void @nested_if_else_if(i32 addrspace(1)* nocapture %arg) {
171 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
172 %tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
173 store i32 0, i32 addrspace(1)* %tmp1, align 4
174 %cc1 = icmp ugt i32 %tmp, 1
175 br i1 %cc1, label %bb.outer.then, label %bb.outer.else
178 %tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 1
179 store i32 1, i32 addrspace(1)* %tmp2, align 4
180 %cc2 = icmp eq i32 %tmp, 2
181 br i1 %cc2, label %bb.inner.then, label %bb.outer.end
184 %tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 2
185 store i32 2, i32 addrspace(1)* %tmp3, align 4
186 br label %bb.outer.end
189 %tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 3
190 store i32 3, i32 addrspace(1)* %tmp4, align 4
191 %cc3 = icmp eq i32 %tmp, 2
192 br i1 %cc3, label %bb.inner.then2, label %bb.outer.end
195 %tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 4
196 store i32 4, i32 addrspace(1)* %tmp5, align 4
197 br label %bb.outer.end
200 store i32 3, i32 addrspace(3)* null
204 ; ALL-LABEL: {{^}}s_endpgm_unsafe_barrier:
205 ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
206 ; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9_]+]]
207 ; GCN-NEXT: s_cbranch_execz [[ENDIF]]
208 ; GCN-NEXT: {{^BB[0-9_]+}}:
210 ; GCN-NEXT: {{^}}[[ENDIF]]:
211 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
214 define amdgpu_kernel void @s_endpgm_unsafe_barrier(i32 addrspace(1)* nocapture %arg) {
216 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
217 %tmp1 = icmp ugt i32 %tmp, 1
218 br i1 %tmp1, label %bb.then, label %bb.end
220 bb.then: ; preds = %bb
221 %tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
222 store i32 0, i32 addrspace(1)* %tmp4, align 4
225 bb.end: ; preds = %bb.then, %bb
226 call void @llvm.amdgcn.s.barrier()
230 ; Make sure scc liveness is updated if sor_b64 is removed
231 ; ALL-LABEL: {{^}}scc_liveness:
234 ; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}
236 ; GCN-NEXT: s_cbranch_execz
238 ; GCN: [[BB1_LOOP:BB[0-9]+_[0-9]+]]:
239 ; GCN: s_andn2_b64 exec, exec,
240 ; GCN-NEXT: s_cbranch_execnz [[BB1_LOOP]]
242 ; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen
243 ; GCN: s_and_b64 exec, exec, {{vcc|s\[[0-9:]+\]}}
245 ; GCN-NOT: s_or_b64 exec, exec
247 ; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}
248 ; GCN: buffer_store_dword
249 ; GCN: buffer_store_dword
250 ; GCN: buffer_store_dword
251 ; GCN: buffer_store_dword
253 define void @scc_liveness(i32 %arg) local_unnamed_addr #0 {
257 bb1: ; preds = %Flow1, %bb1, %bb
258 %tmp = icmp slt i32 %arg, 519
259 br i1 %tmp, label %bb2, label %bb1
262 %tmp3 = icmp eq i32 %arg, 0
263 br i1 %tmp3, label %bb4, label %bb10
266 %tmp6 = load float, float addrspace(5)* undef
267 %tmp7 = fcmp olt float %tmp6, 0.0
268 br i1 %tmp7, label %bb8, label %Flow
271 %tmp9 = insertelement <4 x float> undef, float 0.0, i32 1
274 Flow: ; preds = %bb8, %bb4
275 %tmp8 = phi <4 x float> [ %tmp9, %bb8 ], [ zeroinitializer, %bb4 ]
278 bb10: ; preds = %Flow, %bb2
279 %tmp11 = phi <4 x float> [ zeroinitializer, %bb2 ], [ %tmp8, %Flow ]
280 br i1 %tmp3, label %bb12, label %Flow1
282 Flow1: ; preds = %bb10
285 bb12: ; preds = %bb10
286 store volatile <4 x float> %tmp11, <4 x float> addrspace(5)* undef, align 16
290 declare i32 @llvm.amdgcn.workitem.id.x() #0
291 declare void @llvm.amdgcn.s.barrier() #1
293 attributes #0 = { nounwind readnone speculatable }
294 attributes #1 = { nounwind convergent }
295 attributes #2 = { nounwind }