1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3 ; GCN-LABEL: {{^}}and_i1_sext_bool:
4 ; GCN: v_cmp_{{gt|le}}_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
5 ; GCN: v_cndmask_b32_e{{32|64}} [[VAL:v[0-9]+]], 0, v{{[0-9]+}}, [[CC]]
6 ; GCN: store_dword {{.*}}[[VAL]]
7 ; GCN-NOT: v_cndmask_b32_e64 v{{[0-9]+}}, {{0|-1}}, {{0|-1}}
8 ; GCN-NOT: v_and_b32_e32
10 define amdgpu_kernel void @and_i1_sext_bool(i32 addrspace(1)* nocapture %arg) {
12 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
13 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
14 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
15 %v = load i32, i32 addrspace(1)* %gep, align 4
16 %cmp = icmp ugt i32 %x, %y
17 %ext = sext i1 %cmp to i32
18 %and = and i32 %v, %ext
19 store i32 %and, i32 addrspace(1)* %gep, align 4
23 declare i32 @llvm.amdgcn.workitem.id.x() #0
25 declare i32 @llvm.amdgcn.workitem.id.y() #0
27 attributes #0 = { nounwind readnone speculatable }