1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
5 define amdgpu_ps float @main(float %arg0, float %arg1) #0 {
8 ; SI-NEXT: v_cvt_i32_f32_e32 v0, v0
9 ; SI-NEXT: s_mov_b32 s0, 0
10 ; SI-NEXT: s_mov_b32 s1, s0
11 ; SI-NEXT: s_mov_b32 s2, s0
12 ; SI-NEXT: s_mov_b32 s3, s0
13 ; SI-NEXT: s_mov_b32 s4, s0
14 ; SI-NEXT: s_mov_b32 s5, s0
15 ; SI-NEXT: s_mov_b32 s6, s0
16 ; SI-NEXT: s_mov_b32 s7, s0
17 ; SI-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm
18 ; SI-NEXT: v_and_b32_e32 v0, 7, v0
19 ; SI-NEXT: s_waitcnt vmcnt(0)
20 ; SI-NEXT: v_lshrrev_b32_e32 v0, v0, v2
21 ; SI-NEXT: v_and_b32_e32 v0, 1, v0
22 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
23 ; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
24 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v0, s0, v0
25 ; SI-NEXT: ; return to shader part epilog
29 ; VI-NEXT: v_cvt_i32_f32_e32 v0, v0
30 ; VI-NEXT: s_mov_b32 s0, 0
31 ; VI-NEXT: s_mov_b32 s1, s0
32 ; VI-NEXT: s_mov_b32 s2, s0
33 ; VI-NEXT: s_mov_b32 s3, s0
34 ; VI-NEXT: s_mov_b32 s4, s0
35 ; VI-NEXT: s_mov_b32 s5, s0
36 ; VI-NEXT: s_mov_b32 s6, s0
37 ; VI-NEXT: s_mov_b32 s7, s0
38 ; VI-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm
39 ; VI-NEXT: v_and_b32_e32 v0, 7, v0
40 ; VI-NEXT: s_waitcnt vmcnt(0)
41 ; VI-NEXT: v_lshrrev_b32_e32 v0, v0, v2
42 ; VI-NEXT: v_and_b32_e32 v0, 1, v0
43 ; VI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
44 ; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
45 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, s0, v0
46 ; VI-NEXT: ; return to shader part epilog
48 %tmp = fptosi float %arg0 to i32
49 %tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 undef, <8 x i32> undef, i32 0, i32 0)
50 %tmp2.f = extractelement <4 x float> %tmp1, i32 0
51 %tmp2 = bitcast float %tmp2.f to i32
52 %tmp3 = and i32 %tmp, 7
53 %tmp4 = shl i32 1, %tmp3
54 %tmp5 = and i32 %tmp2, %tmp4
55 %tmp6 = icmp eq i32 %tmp5, 0
56 %tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg1
57 %tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp7)
58 %tmp9 = bitcast <2 x half> %tmp8 to float
62 declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
63 declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #2
65 attributes #0 = { nounwind }
66 attributes #1 = { nounwind readnone }
67 attributes #2 = { nounwind readonly }