1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s -allow-deprecated-dag-overlap -check-prefixes=GCN,SI
3 ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -allow-deprecated-dag-overlap -check-prefixes=GCN,VI
5 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
6 declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
8 define amdgpu_kernel void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
9 ; SI-LABEL: load_i8_to_f32:
11 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
12 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
13 ; SI-NEXT: s_mov_b32 s7, 0xf000
14 ; SI-NEXT: v_mov_b32_e32 v1, 0
15 ; SI-NEXT: s_mov_b32 s2, 0
16 ; SI-NEXT: s_mov_b32 s3, s7
17 ; SI-NEXT: s_waitcnt lgkmcnt(0)
18 ; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64
19 ; SI-NEXT: s_mov_b32 s6, -1
20 ; SI-NEXT: s_waitcnt vmcnt(0)
21 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
22 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
25 ; VI-LABEL: load_i8_to_f32:
27 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
28 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
29 ; VI-NEXT: s_mov_b32 s7, 0xf000
30 ; VI-NEXT: s_mov_b32 s6, -1
31 ; VI-NEXT: s_waitcnt lgkmcnt(0)
32 ; VI-NEXT: v_mov_b32_e32 v1, s1
33 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
34 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
35 ; VI-NEXT: flat_load_ubyte v0, v[0:1]
36 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
37 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
38 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
40 %tid = call i32 @llvm.amdgcn.workitem.id.x()
41 %gep = getelementptr i8, i8 addrspace(1)* %in, i32 %tid
42 %load = load i8, i8 addrspace(1)* %gep, align 1
43 %cvt = uitofp i8 %load to float
44 store float %cvt, float addrspace(1)* %out, align 4
48 define amdgpu_kernel void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind {
49 ; SI-LABEL: load_v2i8_to_v2f32:
51 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
52 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
53 ; SI-NEXT: s_mov_b32 s7, 0xf000
54 ; SI-NEXT: s_mov_b32 s2, 0
55 ; SI-NEXT: s_mov_b32 s3, s7
56 ; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
57 ; SI-NEXT: v_mov_b32_e32 v1, 0
58 ; SI-NEXT: s_waitcnt lgkmcnt(0)
59 ; SI-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64
60 ; SI-NEXT: s_mov_b32 s6, -1
61 ; SI-NEXT: s_waitcnt vmcnt(0)
62 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
63 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
64 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
67 ; VI-LABEL: load_v2i8_to_v2f32:
69 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
70 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
71 ; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
72 ; VI-NEXT: s_mov_b32 s7, 0xf000
73 ; VI-NEXT: s_mov_b32 s6, -1
74 ; VI-NEXT: s_waitcnt lgkmcnt(0)
75 ; VI-NEXT: v_mov_b32_e32 v1, s1
76 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
77 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
78 ; VI-NEXT: flat_load_ushort v0, v[0:1]
79 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
80 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
81 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
82 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
84 %tid = call i32 @llvm.amdgcn.workitem.id.x()
85 %gep = getelementptr <2 x i8>, <2 x i8> addrspace(1)* %in, i32 %tid
86 %load = load <2 x i8>, <2 x i8> addrspace(1)* %gep, align 2
87 %cvt = uitofp <2 x i8> %load to <2 x float>
88 store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16
92 define amdgpu_kernel void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind {
93 ; SI-LABEL: load_v3i8_to_v3f32:
95 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
96 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
97 ; SI-NEXT: s_mov_b32 s7, 0xf000
98 ; SI-NEXT: s_mov_b32 s2, 0
99 ; SI-NEXT: s_mov_b32 s3, s7
100 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
101 ; SI-NEXT: v_mov_b32_e32 v1, 0
102 ; SI-NEXT: s_waitcnt lgkmcnt(0)
103 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
104 ; SI-NEXT: s_mov_b32 s6, -1
105 ; SI-NEXT: s_waitcnt vmcnt(0)
106 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v2
107 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v2
108 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v2
109 ; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
110 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
113 ; VI-LABEL: load_v3i8_to_v3f32:
115 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
116 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
117 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
118 ; VI-NEXT: s_mov_b32 s7, 0xf000
119 ; VI-NEXT: s_mov_b32 s6, -1
120 ; VI-NEXT: s_waitcnt lgkmcnt(0)
121 ; VI-NEXT: v_mov_b32_e32 v1, s1
122 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
123 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
124 ; VI-NEXT: flat_load_dword v0, v[0:1]
125 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
126 ; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
127 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
128 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
129 ; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[4:7], 0
131 %tid = call i32 @llvm.amdgcn.workitem.id.x()
132 %gep = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %in, i32 %tid
133 %load = load <3 x i8>, <3 x i8> addrspace(1)* %gep, align 4
134 %cvt = uitofp <3 x i8> %load to <3 x float>
135 store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16
139 define amdgpu_kernel void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
140 ; SI-LABEL: load_v4i8_to_v4f32:
142 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
143 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
144 ; SI-NEXT: s_mov_b32 s7, 0xf000
145 ; SI-NEXT: s_mov_b32 s2, 0
146 ; SI-NEXT: s_mov_b32 s3, s7
147 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
148 ; SI-NEXT: v_mov_b32_e32 v1, 0
149 ; SI-NEXT: s_waitcnt lgkmcnt(0)
150 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
151 ; SI-NEXT: s_mov_b32 s6, -1
152 ; SI-NEXT: s_waitcnt vmcnt(0)
153 ; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
154 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
155 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
156 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
157 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
160 ; VI-LABEL: load_v4i8_to_v4f32:
162 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
163 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
164 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
165 ; VI-NEXT: s_mov_b32 s7, 0xf000
166 ; VI-NEXT: s_mov_b32 s6, -1
167 ; VI-NEXT: s_waitcnt lgkmcnt(0)
168 ; VI-NEXT: v_mov_b32_e32 v1, s1
169 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
170 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
171 ; VI-NEXT: flat_load_dword v0, v[0:1]
172 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
173 ; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
174 ; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
175 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
176 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
177 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
179 %tid = call i32 @llvm.amdgcn.workitem.id.x()
180 %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid
181 %load = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
182 %cvt = uitofp <4 x i8> %load to <4 x float>
183 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
187 ; This should not be adding instructions to shift into the correct
188 ; position in the word for the component.
190 ; FIXME: Packing bytes
191 define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
192 ; SI-LABEL: load_v4i8_to_v4f32_unaligned:
194 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
195 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
196 ; SI-NEXT: s_mov_b32 s7, 0xf000
197 ; SI-NEXT: s_mov_b32 s2, 0
198 ; SI-NEXT: s_mov_b32 s3, s7
199 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
200 ; SI-NEXT: v_mov_b32_e32 v1, 0
201 ; SI-NEXT: s_waitcnt lgkmcnt(0)
202 ; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64
203 ; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1
204 ; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:2
205 ; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:3
206 ; SI-NEXT: s_mov_b32 s6, -1
207 ; SI-NEXT: s_waitcnt vmcnt(2)
208 ; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v3
209 ; SI-NEXT: v_or_b32_e32 v1, v1, v2
210 ; SI-NEXT: s_waitcnt vmcnt(0)
211 ; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
212 ; SI-NEXT: v_or_b32_e32 v0, v0, v4
213 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
214 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
215 ; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
216 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
217 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
218 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
219 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
222 ; VI-LABEL: load_v4i8_to_v4f32_unaligned:
224 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
225 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
226 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
227 ; VI-NEXT: s_mov_b32 s7, 0xf000
228 ; VI-NEXT: s_mov_b32 s6, -1
229 ; VI-NEXT: s_waitcnt lgkmcnt(0)
230 ; VI-NEXT: v_mov_b32_e32 v1, s1
231 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
232 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
233 ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v0
234 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
235 ; VI-NEXT: v_add_u32_e32 v4, vcc, 2, v0
236 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
237 ; VI-NEXT: v_add_u32_e32 v6, vcc, 1, v0
238 ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
239 ; VI-NEXT: flat_load_ubyte v0, v[0:1]
240 ; VI-NEXT: flat_load_ubyte v1, v[6:7]
241 ; VI-NEXT: flat_load_ubyte v4, v[4:5]
242 ; VI-NEXT: flat_load_ubyte v2, v[2:3]
243 ; VI-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)
244 ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
245 ; VI-NEXT: v_or_b32_e32 v0, v1, v0
246 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
247 ; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
248 ; VI-NEXT: v_or_b32_e32 v2, v2, v4
249 ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
250 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
251 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
252 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
253 ; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v3
254 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
256 %tid = call i32 @llvm.amdgcn.workitem.id.x()
257 %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid
258 %load = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 1
259 %cvt = uitofp <4 x i8> %load to <4 x float>
260 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
264 ; FIXME: Need to handle non-uniform case for function below (load without gep).
265 ; Instructions still emitted to repack bytes for add use.
266 define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {
267 ; SI-LABEL: load_v4i8_to_v4f32_2_uses:
269 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
270 ; SI-NEXT: s_mov_b32 s3, 0xf000
271 ; SI-NEXT: s_mov_b32 s6, 0
272 ; SI-NEXT: s_mov_b32 s7, s3
273 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
274 ; SI-NEXT: v_mov_b32_e32 v1, 0
275 ; SI-NEXT: s_waitcnt lgkmcnt(0)
276 ; SI-NEXT: buffer_load_dword v1, v[0:1], s[4:7], 0 addr64
277 ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
278 ; SI-NEXT: s_mov_b32 s2, -1
279 ; SI-NEXT: s_movk_i32 s12, 0xff
280 ; SI-NEXT: s_mov_b32 s10, s2
281 ; SI-NEXT: s_mov_b32 s11, s3
282 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
283 ; SI-NEXT: s_waitcnt vmcnt(0)
284 ; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
285 ; SI-NEXT: v_add_i32_e32 v7, vcc, 9, v1
286 ; SI-NEXT: v_and_b32_e32 v6, 0xff00, v1
287 ; SI-NEXT: v_lshrrev_b32_e32 v5, 24, v1
288 ; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v1
289 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v1
290 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v1
291 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v6
292 ; SI-NEXT: v_and_b32_e32 v7, s12, v7
293 ; SI-NEXT: v_add_i32_e32 v4, vcc, 9, v4
294 ; SI-NEXT: s_waitcnt lgkmcnt(0)
295 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
296 ; SI-NEXT: s_waitcnt expcnt(0)
297 ; SI-NEXT: v_or_b32_e32 v0, v6, v7
298 ; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
299 ; SI-NEXT: v_and_b32_e32 v1, s12, v4
300 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x900, v0
301 ; SI-NEXT: v_or_b32_e32 v1, v5, v1
302 ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
303 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
304 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
305 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x9000000, v0
306 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
309 ; VI-LABEL: load_v4i8_to_v4f32_2_uses:
311 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
312 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
313 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
314 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
315 ; VI-NEXT: v_mov_b32_e32 v4, 9
316 ; VI-NEXT: s_waitcnt lgkmcnt(0)
317 ; VI-NEXT: v_mov_b32_e32 v1, s3
318 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
319 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
320 ; VI-NEXT: flat_load_dword v5, v[0:1]
321 ; VI-NEXT: s_mov_b32 s3, 0xf000
322 ; VI-NEXT: s_mov_b32 s2, -1
323 ; VI-NEXT: s_mov_b32 s6, s2
324 ; VI-NEXT: s_mov_b32 s7, s3
325 ; VI-NEXT: s_movk_i32 s8, 0x900
326 ; VI-NEXT: v_mov_b32_e32 v6, s8
327 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
328 ; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v5
329 ; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v5
330 ; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v5
331 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v5
332 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v5
333 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
334 ; VI-NEXT: v_and_b32_e32 v8, 0xffffff00, v5
335 ; VI-NEXT: v_add_u16_e32 v9, 9, v5
336 ; VI-NEXT: v_add_u16_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
337 ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v7
338 ; VI-NEXT: v_or_b32_sdwa v0, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
339 ; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
340 ; VI-NEXT: v_add_u16_e32 v0, s8, v0
341 ; VI-NEXT: v_add_u16_sdwa v1, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
342 ; VI-NEXT: v_or_b32_e32 v0, v0, v1
343 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
345 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
346 %in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
347 %load = load <4 x i8>, <4 x i8> addrspace(1)* %in.ptr, align 4
348 %cvt = uitofp <4 x i8> %load to <4 x float>
349 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
350 %add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load
351 store <4 x i8> %add, <4 x i8> addrspace(1)* %out2, align 4
355 ; Make sure this doesn't crash.
356 define amdgpu_kernel void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {
357 ; SI-LABEL: load_v7i8_to_v7f32:
359 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
360 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
361 ; SI-NEXT: s_mov_b32 s7, 0xf000
362 ; SI-NEXT: s_mov_b32 s2, 0
363 ; SI-NEXT: s_mov_b32 s3, s7
364 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
365 ; SI-NEXT: v_mov_b32_e32 v1, 0
366 ; SI-NEXT: s_waitcnt lgkmcnt(0)
367 ; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64
368 ; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1
369 ; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:2
370 ; SI-NEXT: buffer_load_ubyte v5, v[0:1], s[0:3], 0 addr64 offset:3
371 ; SI-NEXT: buffer_load_ubyte v6, v[0:1], s[0:3], 0 addr64 offset:4
372 ; SI-NEXT: buffer_load_ubyte v7, v[0:1], s[0:3], 0 addr64 offset:5
373 ; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:6
374 ; SI-NEXT: s_mov_b32 s6, -1
375 ; SI-NEXT: s_waitcnt vmcnt(5)
376 ; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v3
377 ; SI-NEXT: v_or_b32_e32 v1, v1, v2
378 ; SI-NEXT: s_waitcnt vmcnt(3)
379 ; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
380 ; SI-NEXT: v_or_b32_e32 v2, v2, v4
381 ; SI-NEXT: s_waitcnt vmcnt(1)
382 ; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v7
383 ; SI-NEXT: s_waitcnt vmcnt(0)
384 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
385 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:24
386 ; SI-NEXT: s_waitcnt expcnt(0)
387 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
388 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
389 ; SI-NEXT: v_or_b32_e32 v4, v3, v6
390 ; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
391 ; SI-NEXT: v_or_b32_e32 v4, v4, v5
392 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v5, v4
393 ; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
394 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
395 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
396 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
397 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v4
398 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
399 ; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[4:7], 0 offset:16
402 ; VI-LABEL: load_v7i8_to_v7f32:
404 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
405 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
406 ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
407 ; VI-NEXT: s_mov_b32 s7, 0xf000
408 ; VI-NEXT: s_mov_b32 s6, -1
409 ; VI-NEXT: s_waitcnt lgkmcnt(0)
410 ; VI-NEXT: v_mov_b32_e32 v1, s1
411 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
412 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
413 ; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0
414 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
415 ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v0
416 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
417 ; VI-NEXT: flat_load_ubyte v10, v[4:5]
418 ; VI-NEXT: flat_load_ubyte v11, v[2:3]
419 ; VI-NEXT: v_add_u32_e32 v2, vcc, 2, v0
420 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
421 ; VI-NEXT: v_add_u32_e32 v4, vcc, 5, v0
422 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
423 ; VI-NEXT: v_add_u32_e32 v6, vcc, 4, v0
424 ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
425 ; VI-NEXT: v_add_u32_e32 v8, vcc, 6, v0
426 ; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
427 ; VI-NEXT: flat_load_ubyte v0, v[0:1]
428 ; VI-NEXT: flat_load_ubyte v1, v[8:9]
429 ; VI-NEXT: flat_load_ubyte v7, v[6:7]
430 ; VI-NEXT: flat_load_ubyte v4, v[4:5]
431 ; VI-NEXT: flat_load_ubyte v2, v[2:3]
432 ; VI-NEXT: s_waitcnt vmcnt(6) lgkmcnt(6)
433 ; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v10
434 ; VI-NEXT: s_waitcnt vmcnt(5) lgkmcnt(5)
435 ; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v11
436 ; VI-NEXT: s_waitcnt vmcnt(4) lgkmcnt(4)
437 ; VI-NEXT: v_or_b32_e32 v0, v3, v0
438 ; VI-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)
439 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v6, v1
440 ; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
441 ; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
442 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
443 ; VI-NEXT: v_or_b32_sdwa v1, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
444 ; VI-NEXT: v_or_b32_e32 v0, v1, v0
445 ; VI-NEXT: v_or_b32_e32 v4, v4, v7
446 ; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
447 ; VI-NEXT: v_or_b32_e32 v4, v4, v5
448 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v5, v4
449 ; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
450 ; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
451 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
452 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
453 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v4, v4
454 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
455 ; VI-NEXT: buffer_store_dwordx3 v[4:6], off, s[4:7], 0 offset:16
457 %tid = call i32 @llvm.amdgcn.workitem.id.x()
458 %gep = getelementptr <7 x i8>, <7 x i8> addrspace(1)* %in, i32 %tid
459 %load = load <7 x i8>, <7 x i8> addrspace(1)* %gep, align 1
460 %cvt = uitofp <7 x i8> %load to <7 x float>
461 store <7 x float> %cvt, <7 x float> addrspace(1)* %out, align 16
465 define amdgpu_kernel void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind {
466 ; SI-LABEL: load_v8i8_to_v8f32:
468 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
469 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
470 ; SI-NEXT: s_mov_b32 s7, 0xf000
471 ; SI-NEXT: s_mov_b32 s2, 0
472 ; SI-NEXT: s_mov_b32 s3, s7
473 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
474 ; SI-NEXT: v_mov_b32_e32 v1, 0
475 ; SI-NEXT: s_waitcnt lgkmcnt(0)
476 ; SI-NEXT: buffer_load_dwordx2 v[7:8], v[0:1], s[0:3], 0 addr64
477 ; SI-NEXT: s_mov_b32 s6, -1
478 ; SI-NEXT: s_waitcnt vmcnt(0)
479 ; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v7
480 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v7
481 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v7
482 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v7
483 ; SI-NEXT: v_cvt_f32_ubyte3_e32 v7, v8
484 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v6, v8
485 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v5, v8
486 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v8
487 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
488 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
491 ; VI-LABEL: load_v8i8_to_v8f32:
493 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
494 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
495 ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
496 ; VI-NEXT: s_mov_b32 s7, 0xf000
497 ; VI-NEXT: s_mov_b32 s6, -1
498 ; VI-NEXT: s_waitcnt lgkmcnt(0)
499 ; VI-NEXT: v_mov_b32_e32 v1, s1
500 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
501 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
502 ; VI-NEXT: flat_load_dwordx2 v[7:8], v[0:1]
503 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
504 ; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v7
505 ; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v7
506 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v7
507 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v7
508 ; VI-NEXT: v_cvt_f32_ubyte3_e32 v7, v8
509 ; VI-NEXT: v_cvt_f32_ubyte2_e32 v6, v8
510 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v5, v8
511 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v4, v8
512 ; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
513 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
515 %tid = call i32 @llvm.amdgcn.workitem.id.x()
516 %gep = getelementptr <8 x i8>, <8 x i8> addrspace(1)* %in, i32 %tid
517 %load = load <8 x i8>, <8 x i8> addrspace(1)* %gep, align 8
518 %cvt = uitofp <8 x i8> %load to <8 x float>
519 store <8 x float> %cvt, <8 x float> addrspace(1)* %out, align 16
523 define amdgpu_kernel void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
524 ; SI-LABEL: i8_zext_inreg_i32_to_f32:
526 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
527 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
528 ; SI-NEXT: s_mov_b32 s7, 0xf000
529 ; SI-NEXT: s_mov_b32 s2, 0
530 ; SI-NEXT: s_mov_b32 s3, s7
531 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
532 ; SI-NEXT: v_mov_b32_e32 v1, 0
533 ; SI-NEXT: s_waitcnt lgkmcnt(0)
534 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
535 ; SI-NEXT: s_mov_b32 s6, -1
536 ; SI-NEXT: s_waitcnt vmcnt(0)
537 ; SI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
538 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
539 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
542 ; VI-LABEL: i8_zext_inreg_i32_to_f32:
544 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
545 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
546 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
547 ; VI-NEXT: s_mov_b32 s7, 0xf000
548 ; VI-NEXT: s_mov_b32 s6, -1
549 ; VI-NEXT: s_waitcnt lgkmcnt(0)
550 ; VI-NEXT: v_mov_b32_e32 v1, s1
551 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
552 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
553 ; VI-NEXT: flat_load_dword v0, v[0:1]
554 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
555 ; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
556 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
557 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
559 %tid = call i32 @llvm.amdgcn.workitem.id.x()
560 %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
561 %load = load i32, i32 addrspace(1)* %gep, align 4
562 %add = add i32 %load, 2
563 %inreg = and i32 %add, 255
564 %cvt = uitofp i32 %inreg to float
565 store float %cvt, float addrspace(1)* %out, align 4
569 define amdgpu_kernel void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
570 ; SI-LABEL: i8_zext_inreg_hi1_to_f32:
572 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
573 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
574 ; SI-NEXT: s_mov_b32 s7, 0xf000
575 ; SI-NEXT: s_mov_b32 s2, 0
576 ; SI-NEXT: s_mov_b32 s3, s7
577 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
578 ; SI-NEXT: v_mov_b32_e32 v1, 0
579 ; SI-NEXT: s_waitcnt lgkmcnt(0)
580 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
581 ; SI-NEXT: s_mov_b32 s6, -1
582 ; SI-NEXT: s_waitcnt vmcnt(0)
583 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
584 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
587 ; VI-LABEL: i8_zext_inreg_hi1_to_f32:
589 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
590 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
591 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
592 ; VI-NEXT: s_mov_b32 s7, 0xf000
593 ; VI-NEXT: s_mov_b32 s6, -1
594 ; VI-NEXT: s_waitcnt lgkmcnt(0)
595 ; VI-NEXT: v_mov_b32_e32 v1, s1
596 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
597 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
598 ; VI-NEXT: flat_load_dword v0, v[0:1]
599 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
600 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
601 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
603 %tid = call i32 @llvm.amdgcn.workitem.id.x()
604 %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
605 %load = load i32, i32 addrspace(1)* %gep, align 4
606 %inreg = and i32 %load, 65280
607 %shr = lshr i32 %inreg, 8
608 %cvt = uitofp i32 %shr to float
609 store float %cvt, float addrspace(1)* %out, align 4
613 ; We don't get these ones because of the zext, but instcombine removes
614 ; them so it shouldn't really matter.
615 define amdgpu_kernel void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
616 ; SI-LABEL: i8_zext_i32_to_f32:
618 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
619 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
620 ; SI-NEXT: s_mov_b32 s7, 0xf000
621 ; SI-NEXT: v_mov_b32_e32 v1, 0
622 ; SI-NEXT: s_mov_b32 s2, 0
623 ; SI-NEXT: s_mov_b32 s3, s7
624 ; SI-NEXT: s_waitcnt lgkmcnt(0)
625 ; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64
626 ; SI-NEXT: s_mov_b32 s6, -1
627 ; SI-NEXT: s_waitcnt vmcnt(0)
628 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
629 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
632 ; VI-LABEL: i8_zext_i32_to_f32:
634 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
635 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
636 ; VI-NEXT: s_mov_b32 s7, 0xf000
637 ; VI-NEXT: s_mov_b32 s6, -1
638 ; VI-NEXT: s_waitcnt lgkmcnt(0)
639 ; VI-NEXT: v_mov_b32_e32 v1, s1
640 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
641 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
642 ; VI-NEXT: flat_load_ubyte v0, v[0:1]
643 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
644 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
645 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
647 %tid = call i32 @llvm.amdgcn.workitem.id.x()
648 %gep = getelementptr i8, i8 addrspace(1)* %in, i32 %tid
649 %load = load i8, i8 addrspace(1)* %gep, align 1
650 %ext = zext i8 %load to i32
651 %cvt = uitofp i32 %ext to float
652 store float %cvt, float addrspace(1)* %out, align 4
656 define amdgpu_kernel void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
657 ; SI-LABEL: v4i8_zext_v4i32_to_v4f32:
659 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
660 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
661 ; SI-NEXT: s_mov_b32 s7, 0xf000
662 ; SI-NEXT: s_mov_b32 s2, 0
663 ; SI-NEXT: s_mov_b32 s3, s7
664 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
665 ; SI-NEXT: v_mov_b32_e32 v1, 0
666 ; SI-NEXT: s_waitcnt lgkmcnt(0)
667 ; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64
668 ; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1
669 ; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:2
670 ; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:3
671 ; SI-NEXT: s_mov_b32 s6, -1
672 ; SI-NEXT: s_waitcnt vmcnt(2)
673 ; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v3
674 ; SI-NEXT: v_or_b32_e32 v1, v1, v2
675 ; SI-NEXT: s_waitcnt vmcnt(0)
676 ; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
677 ; SI-NEXT: v_or_b32_e32 v0, v0, v4
678 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
679 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
680 ; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
681 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
682 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
683 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
684 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
687 ; VI-LABEL: v4i8_zext_v4i32_to_v4f32:
689 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
690 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
691 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
692 ; VI-NEXT: s_mov_b32 s7, 0xf000
693 ; VI-NEXT: s_mov_b32 s6, -1
694 ; VI-NEXT: s_waitcnt lgkmcnt(0)
695 ; VI-NEXT: v_mov_b32_e32 v1, s1
696 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
697 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
698 ; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0
699 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
700 ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v0
701 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
702 ; VI-NEXT: v_add_u32_e32 v6, vcc, 2, v0
703 ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
704 ; VI-NEXT: flat_load_ubyte v0, v[0:1]
705 ; VI-NEXT: flat_load_ubyte v1, v[6:7]
706 ; VI-NEXT: flat_load_ubyte v4, v[4:5]
707 ; VI-NEXT: flat_load_ubyte v2, v[2:3]
708 ; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
709 ; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
710 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
711 ; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
712 ; VI-NEXT: v_or_b32_e32 v4, v2, v0
713 ; VI-NEXT: v_or_b32_sdwa v0, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
714 ; VI-NEXT: v_or_b32_e32 v0, v0, v4
715 ; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
716 ; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
717 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
718 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
719 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
721 %tid = call i32 @llvm.amdgcn.workitem.id.x()
722 %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid
723 %load = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 1
724 %ext = zext <4 x i8> %load to <4 x i32>
725 %cvt = uitofp <4 x i32> %ext to <4 x float>
726 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
730 define amdgpu_kernel void @extract_byte0_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
731 ; SI-LABEL: extract_byte0_to_f32:
733 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
734 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
735 ; SI-NEXT: s_mov_b32 s7, 0xf000
736 ; SI-NEXT: s_mov_b32 s2, 0
737 ; SI-NEXT: s_mov_b32 s3, s7
738 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
739 ; SI-NEXT: v_mov_b32_e32 v1, 0
740 ; SI-NEXT: s_waitcnt lgkmcnt(0)
741 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
742 ; SI-NEXT: s_mov_b32 s6, -1
743 ; SI-NEXT: s_waitcnt vmcnt(0)
744 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
745 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
748 ; VI-LABEL: extract_byte0_to_f32:
750 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
751 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
752 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
753 ; VI-NEXT: s_mov_b32 s7, 0xf000
754 ; VI-NEXT: s_mov_b32 s6, -1
755 ; VI-NEXT: s_waitcnt lgkmcnt(0)
756 ; VI-NEXT: v_mov_b32_e32 v1, s1
757 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
758 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
759 ; VI-NEXT: flat_load_dword v0, v[0:1]
760 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
761 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
762 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
764 %tid = call i32 @llvm.amdgcn.workitem.id.x()
765 %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
766 %val = load i32, i32 addrspace(1)* %gep
767 %and = and i32 %val, 255
768 %cvt = uitofp i32 %and to float
769 store float %cvt, float addrspace(1)* %out
773 define amdgpu_kernel void @extract_byte1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
774 ; SI-LABEL: extract_byte1_to_f32:
776 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
777 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
778 ; SI-NEXT: s_mov_b32 s7, 0xf000
779 ; SI-NEXT: s_mov_b32 s2, 0
780 ; SI-NEXT: s_mov_b32 s3, s7
781 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
782 ; SI-NEXT: v_mov_b32_e32 v1, 0
783 ; SI-NEXT: s_waitcnt lgkmcnt(0)
784 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
785 ; SI-NEXT: s_mov_b32 s6, -1
786 ; SI-NEXT: s_waitcnt vmcnt(0)
787 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
788 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
791 ; VI-LABEL: extract_byte1_to_f32:
793 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
794 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
795 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
796 ; VI-NEXT: s_mov_b32 s7, 0xf000
797 ; VI-NEXT: s_mov_b32 s6, -1
798 ; VI-NEXT: s_waitcnt lgkmcnt(0)
799 ; VI-NEXT: v_mov_b32_e32 v1, s1
800 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
801 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
802 ; VI-NEXT: flat_load_dword v0, v[0:1]
803 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
804 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
805 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
807 %tid = call i32 @llvm.amdgcn.workitem.id.x()
808 %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
809 %val = load i32, i32 addrspace(1)* %gep
810 %srl = lshr i32 %val, 8
811 %and = and i32 %srl, 255
812 %cvt = uitofp i32 %and to float
813 store float %cvt, float addrspace(1)* %out
817 define amdgpu_kernel void @extract_byte2_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
818 ; SI-LABEL: extract_byte2_to_f32:
820 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
821 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
822 ; SI-NEXT: s_mov_b32 s7, 0xf000
823 ; SI-NEXT: s_mov_b32 s2, 0
824 ; SI-NEXT: s_mov_b32 s3, s7
825 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
826 ; SI-NEXT: v_mov_b32_e32 v1, 0
827 ; SI-NEXT: s_waitcnt lgkmcnt(0)
828 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
829 ; SI-NEXT: s_mov_b32 s6, -1
830 ; SI-NEXT: s_waitcnt vmcnt(0)
831 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
832 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
835 ; VI-LABEL: extract_byte2_to_f32:
837 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
838 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
839 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
840 ; VI-NEXT: s_mov_b32 s7, 0xf000
841 ; VI-NEXT: s_mov_b32 s6, -1
842 ; VI-NEXT: s_waitcnt lgkmcnt(0)
843 ; VI-NEXT: v_mov_b32_e32 v1, s1
844 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
845 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
846 ; VI-NEXT: flat_load_dword v0, v[0:1]
847 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
848 ; VI-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
849 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
851 %tid = call i32 @llvm.amdgcn.workitem.id.x()
852 %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
853 %val = load i32, i32 addrspace(1)* %gep
854 %srl = lshr i32 %val, 16
855 %and = and i32 %srl, 255
856 %cvt = uitofp i32 %and to float
857 store float %cvt, float addrspace(1)* %out
861 define amdgpu_kernel void @extract_byte3_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
862 ; SI-LABEL: extract_byte3_to_f32:
864 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
865 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
866 ; SI-NEXT: s_mov_b32 s7, 0xf000
867 ; SI-NEXT: s_mov_b32 s2, 0
868 ; SI-NEXT: s_mov_b32 s3, s7
869 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
870 ; SI-NEXT: v_mov_b32_e32 v1, 0
871 ; SI-NEXT: s_waitcnt lgkmcnt(0)
872 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
873 ; SI-NEXT: s_mov_b32 s6, -1
874 ; SI-NEXT: s_waitcnt vmcnt(0)
875 ; SI-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
876 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
879 ; VI-LABEL: extract_byte3_to_f32:
881 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
882 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
883 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
884 ; VI-NEXT: s_mov_b32 s7, 0xf000
885 ; VI-NEXT: s_mov_b32 s6, -1
886 ; VI-NEXT: s_waitcnt lgkmcnt(0)
887 ; VI-NEXT: v_mov_b32_e32 v1, s1
888 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
889 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
890 ; VI-NEXT: flat_load_dword v0, v[0:1]
891 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
892 ; VI-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
893 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
895 %tid = call i32 @llvm.amdgcn.workitem.id.x()
896 %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
897 %val = load i32, i32 addrspace(1)* %gep
898 %srl = lshr i32 %val, 24
899 %and = and i32 %srl, 255
900 %cvt = uitofp i32 %and to float
901 store float %cvt, float addrspace(1)* %out
905 define amdgpu_kernel void @cvt_ubyte0_or_multiuse(i32 addrspace(1)* %in, float addrspace(1)* %out) {
906 ; SI-LABEL: cvt_ubyte0_or_multiuse:
908 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
909 ; SI-NEXT: s_mov_b32 s7, 0xf000
910 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
911 ; SI-NEXT: v_mov_b32_e32 v1, 0
912 ; SI-NEXT: s_mov_b32 s6, -1
913 ; SI-NEXT: s_waitcnt lgkmcnt(0)
914 ; SI-NEXT: s_mov_b32 s4, s2
915 ; SI-NEXT: s_mov_b32 s5, s3
916 ; SI-NEXT: s_mov_b32 s2, 0
917 ; SI-NEXT: s_mov_b32 s3, s7
918 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
919 ; SI-NEXT: s_waitcnt vmcnt(0)
920 ; SI-NEXT: v_or_b32_e32 v0, 0x80000001, v0
921 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v0
922 ; SI-NEXT: v_add_f32_e32 v0, v0, v1
923 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
926 ; VI-LABEL: cvt_ubyte0_or_multiuse:
928 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
929 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
930 ; VI-NEXT: s_mov_b32 s7, 0xf000
931 ; VI-NEXT: s_mov_b32 s6, -1
932 ; VI-NEXT: s_waitcnt lgkmcnt(0)
933 ; VI-NEXT: v_mov_b32_e32 v1, s1
934 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
935 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
936 ; VI-NEXT: flat_load_dword v0, v[0:1]
937 ; VI-NEXT: s_mov_b32 s4, s2
938 ; VI-NEXT: s_mov_b32 s5, s3
939 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
940 ; VI-NEXT: v_or_b32_e32 v0, 0x80000001, v0
941 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v0
942 ; VI-NEXT: v_add_f32_e32 v0, v0, v1
943 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
946 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
947 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %lid
948 %load = load i32, i32 addrspace(1)* %gep
949 %or = or i32 %load, -2147483647
950 %and = and i32 %or, 255
951 %uitofp = uitofp i32 %and to float
952 %cast = bitcast i32 %or to float
953 %add = fadd float %cast, %uitofp
954 store float %add, float addrspace(1)* %out