1 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
2 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
4 ; GCN-LABEL: {{^}}dpp_add:
5 ; GCN: global_load_dword [[V:v[0-9]+]],
6 ; GCN: v_add_{{(nc_)?}}u32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
7 define amdgpu_kernel void @dpp_add(i32 addrspace(1)* %arg) {
8 %id = tail call i32 @llvm.amdgcn.workitem.id.x()
9 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
10 %load = load i32, i32 addrspace(1)* %gep
11 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
12 %add = add i32 %tmp0, %load
13 store i32 %add, i32 addrspace(1)* %gep
17 ; GCN-LABEL: {{^}}dpp_ceil:
18 ; GCN: global_load_dword [[V:v[0-9]+]],
19 ; GCN: v_ceil_f32_dpp [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
20 define amdgpu_kernel void @dpp_ceil(i32 addrspace(1)* %arg) {
21 %id = tail call i32 @llvm.amdgcn.workitem.id.x()
22 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
23 %load = load i32, i32 addrspace(1)* %gep
24 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
25 %tmp1 = bitcast i32 %tmp0 to float
26 %round = tail call float @llvm.ceil.f32(float %tmp1)
27 %tmp2 = bitcast float %round to i32
28 store i32 %tmp2, i32 addrspace(1)* %gep
32 ; GCN-LABEL: {{^}}dpp_fadd:
33 ; GCN: global_load_dword [[V:v[0-9]+]],
34 ; GCN: v_add_f32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
35 define amdgpu_kernel void @dpp_fadd(i32 addrspace(1)* %arg) {
36 %id = tail call i32 @llvm.amdgcn.workitem.id.x()
37 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
38 %load = load i32, i32 addrspace(1)* %gep
39 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
40 %tmp1 = bitcast i32 %tmp0 to float
41 %t = bitcast i32 %load to float
42 %add = fadd float %tmp1, %t
43 %tmp2 = bitcast float %add to i32
44 store i32 %tmp2, i32 addrspace(1)* %gep
49 declare i32 @llvm.amdgcn.workitem.id.x()
50 declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0
51 declare float @llvm.ceil.f32(float)
53 attributes #0 = { nounwind readnone convergent }