1 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
4 # old is undefined: only combine when masks are fully enabled and
5 # bound_ctrl:0 is set, otherwise the result of DPP VALU op can be undefined.
6 # GCN-LABEL: name: old_is_undef
7 # GCN: %2:vgpr_32 = IMPLICIT_DEF
9 # GCN: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec
10 # GCN: %6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec
11 # GCN: %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec
12 # GCN: %10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec
14 # GCN: %12:vgpr_32 = V_NOT_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
15 # GCN: %14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec
16 # GCN: %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
17 # GCN: %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
19 tracksRegLiveness: true
22 liveins: $vgpr0, $vgpr1
23 %0:vgpr_32 = COPY $vgpr0
24 %1:vgpr_32 = COPY $vgpr1
25 %2:vgpr_32 = IMPLICIT_DEF
28 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
29 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
31 %5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
32 %6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec
34 %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
35 %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec
37 %9:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
38 %10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec
41 %11:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
42 %12:vgpr_32 = V_NOT_B32_e32 %11, implicit $exec
44 %13:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
45 %14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec
47 %15:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
48 %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
50 %17:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
51 %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
56 # GCN-LABEL: name: old_is_0
59 # case 1: old is zero, masks are fully enabled, bound_ctrl:0 is on:
60 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
61 # out of range}) or active src lane result - can combine with old = undef.
62 # undef is preffered as it makes life easier for the regalloc.
63 # GCN: [[U1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
64 # GCN: %4:vgpr_32 = V_ADD_U32_dpp [[U1]], %0, %1, 1, 15, 15, 1, implicit $exec
66 # case 2: old is zero, masks are fully enabled, bound_ctrl:0 is off:
67 # as the DPP mov old is zero this case is no different from case 1 - combine it
68 # setting bound_ctrl0 on for the combined DPP VALU op to make old undefined
69 # GCN: [[U2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
70 # GCN: %6:vgpr_32 = V_ADD_U32_dpp [[U2]], %0, %1, 1, 15, 15, 1, implicit $exec
72 # case 3: masks are partialy disabled, bound_ctrl:0 is on:
73 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
74 # out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
75 # active src lane result - can combine with old = src1 of the VALU op.
76 # The VALU op should have the same masks as DPP mov as they select lanes
77 # with identity value.
78 # Special case: the bound_ctrl for the combined DPP VALU op isn't important
79 # here but let's make it off to keep the combiner's logic simpler.
80 # GCN: %8:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
82 # case 4: masks are partialy disabled, bound_ctrl:0 is off:
83 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
84 # out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
85 # active src lane result - can combine with old = src1 of the VALU op.
86 # The VALU op should have the same masks as DPP mov as they select
87 # lanes with identity value
88 # GCN: %10:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
92 # GCN: [[U3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
93 # GCN: %12:vgpr_32 = V_NOT_B32_dpp [[U3]], %0, 1, 15, 15, 1, implicit $exec
95 # GCN: [[U4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
96 # GCN: %14:vgpr_32 = V_NOT_B32_dpp [[U4]], %0, 1, 15, 15, 1, implicit $exec
97 # case 3 and 4 not appliable as there is no way to specify unchanged result
98 # for the unary VALU op
99 # GCN: %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
100 # GCN: %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
103 tracksRegLiveness: true
106 liveins: $vgpr0, $vgpr1
107 %0:vgpr_32 = COPY $vgpr0
108 %1:vgpr_32 = COPY $vgpr1
109 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
112 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
113 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
115 %5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
116 %6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec
118 %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
119 %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec
121 %9:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
122 %10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec
125 %11:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
126 %12:vgpr_32 = V_NOT_B32_e32 %11, implicit $exec
128 %13:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
129 %14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec
131 %15:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
132 %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
134 %17:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
135 %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
138 # old is nonzero identity cases:
140 # old is nonzero identity, masks are fully enabled, bound_ctrl:0 is off:
141 # the DPP mov result would be either identity ({src lane disabled}|{out of
142 # range}) or src lane result - can combine with old = src1 of the VALU op
143 # The DPP VALU op should have the same masks (and bctrl) as DPP mov as they
144 # select lanes with identity value
146 # GCN-LABEL: name: nonzero_old_is_identity_masks_enabled_bctl_off
147 # GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec
148 # GCN: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec
149 # GCN: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec
150 # GCN: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec
152 name: nonzero_old_is_identity_masks_enabled_bctl_off
153 tracksRegLiveness: true
156 liveins: $vgpr0, $vgpr1
157 %0:vgpr_32 = COPY $vgpr0
158 %1:vgpr_32 = COPY $vgpr1
160 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
161 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
162 %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
164 %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
165 %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 15, 0, implicit $exec
166 %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
168 %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
169 %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 15, 15, 0, implicit $exec
170 %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
172 %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
173 %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 15, 0, implicit $exec
174 %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
177 # old is nonzero identity, masks are partially enabled, bound_ctrl:0 is off:
178 # the DPP mov result would be either identity ({src lane disabled}|{src lane is
179 # out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
180 # active src lane result - can combine with old = src1 of the VALU op.
181 # The DPP VALU op should have the same masks (and bctrl) as DPP mov as they
182 # select lanes with identity value
184 # GCN-LABEL: name: nonzero_old_is_identity_masks_partially_disabled_bctl_off
185 # GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
186 # GCN: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
187 # GCN: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
188 # GCN: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
190 name: nonzero_old_is_identity_masks_partially_disabled_bctl_off
191 tracksRegLiveness: true
194 liveins: $vgpr0, $vgpr1
195 %0:vgpr_32 = COPY $vgpr0
196 %1:vgpr_32 = COPY $vgpr1
198 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
199 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
200 %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
202 %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
203 %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 0, implicit $exec
204 %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
206 %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
207 %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec
208 %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
210 %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
211 %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec
212 %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
215 # old is nonzero identity, masks are partially enabled, bound_ctrl:0 is on:
216 # the DPP mov result may have 3 different values:
217 # 1. the active src lane result
218 # 2. 0 if the src lane is disabled|out of range
219 # 3. DPP mov's old value if the mov's dest VGPR write is disabled by masks
222 # GCN-LABEL: name: nonzero_old_is_identity_masks_partially_disabled_bctl0
223 # GCN: %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
224 # GCN: %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
225 # GCN: %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
226 # GCN: %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
228 name: nonzero_old_is_identity_masks_partially_disabled_bctl0
229 tracksRegLiveness: true
232 liveins: $vgpr0, $vgpr1
233 %0:vgpr_32 = COPY $vgpr0
234 %1:vgpr_32 = COPY $vgpr1
236 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
237 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
238 %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
240 %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
241 %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 1, implicit $exec
242 %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
244 %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
245 %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 1, implicit $exec
246 %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
248 %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
249 %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 1, implicit $exec
250 %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
253 # when the DPP source isn't a src0 operand the operation should be commuted if possible
254 # GCN-LABEL: name: dpp_commute
255 # GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
256 # GCN: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
257 # GCN: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
258 # GCN: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
259 # GCN: %16:vgpr_32 = V_SUBREV_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
260 # GCN: %19:vgpr_32 = V_ADD_I32_e32 5, %18, implicit-def $vcc, implicit $exec
262 tracksRegLiveness: true
265 liveins: $vgpr0, $vgpr1
267 %0:vgpr_32 = COPY $vgpr0
268 %1:vgpr_32 = COPY $vgpr1
270 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
271 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
272 %4:vgpr_32 = V_MUL_U32_U24_e32 %1, %3, implicit $exec
274 %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
275 %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 0, implicit $exec
276 %7:vgpr_32 = V_AND_B32_e32 %1, %6, implicit $exec
278 %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
279 %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec
280 %10:vgpr_32 = V_MAX_I32_e32 %1, %9, implicit $exec
282 %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
283 %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec
284 %13:vgpr_32 = V_MIN_I32_e32 %1, %12, implicit $exec
286 %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
287 %15:vgpr_32 = V_MOV_B32_dpp %14, %0, 1, 14, 15, 0, implicit $exec
288 %16:vgpr_32 = V_SUB_I32_e32 %1, %15, implicit-def $vcc, implicit $exec
290 ; this cannot be combined because immediate as src0 isn't commutable
291 %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
292 %18:vgpr_32 = V_MOV_B32_dpp %17, %0, 1, 14, 15, 0, implicit $exec
293 %19:vgpr_32 = V_ADD_I32_e32 5, %18, implicit-def $vcc, implicit $exec
296 # check for floating point modifiers
297 # GCN-LABEL: name: add_f32_e64
298 # GCN: %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
299 # GCN: %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $exec
300 # GCN: %6:vgpr_32 = V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $exec
301 # GCN: %8:vgpr_32 = V_ADD_F32_dpp %2, 1, %1, 2, %0, 1, 15, 15, 1, implicit $exec
302 # GCN: %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $exec
305 tracksRegLiveness: true
308 liveins: $vgpr0, $vgpr1
310 %0:vgpr_32 = COPY $vgpr0
311 %1:vgpr_32 = COPY $vgpr1
312 %2:vgpr_32 = IMPLICIT_DEF
314 ; this shouldn't be combined as omod is set
315 %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
316 %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $exec
318 ; this should be combined as all modifiers are default
319 %5:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
320 %6:vgpr_32 = V_ADD_F32_e64 0, %5, 0, %0, 0, 0, implicit $exec
322 ; this should be combined as modifiers other than abs|neg are default
323 %7:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
324 %8:vgpr_32 = V_ADD_F32_e64 1, %7, 2, %0, 0, 0, implicit $exec
326 ; this shouldn't be combined as modifiers aren't abs|neg
327 %9:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
328 %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $exec
331 # check for e64 modifiers
332 # GCN-LABEL: name: add_u32_e64
333 # GCN: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec
334 # GCN: %6:vgpr_32 = V_ADD_U32_e64 %5, %1, 1, implicit $exec
337 tracksRegLiveness: true
340 liveins: $vgpr0, $vgpr1
342 %0:vgpr_32 = COPY $vgpr0
343 %1:vgpr_32 = COPY $vgpr1
344 %2:vgpr_32 = IMPLICIT_DEF
346 ; this should be combined as all modifiers are default
347 %3:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec
348 %4:vgpr_32 = V_ADD_U32_e64 %3, %1, 0, implicit $exec
350 ; this shouldn't be combined as clamp is set
351 %5:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec
352 %6:vgpr_32 = V_ADD_U32_e64 %5, %1, 1, implicit $exec
355 # tests on sequences of dpp consumers
356 # GCN-LABEL: name: dpp_seq
357 # GCN: %4:vgpr_32 = V_ADD_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
358 # GCN: %5:vgpr_32 = V_SUBREV_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
359 # GCN: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
361 # GCN: %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
364 tracksRegLiveness: true
367 liveins: $vgpr0, $vgpr1
368 %0:vgpr_32 = COPY $vgpr0
369 %1:vgpr_32 = COPY $vgpr1
370 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
372 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
373 %4:vgpr_32 = V_ADD_I32_e32 %3, %1, implicit-def $vcc, implicit $exec
374 %5:vgpr_32 = V_SUB_I32_e32 %1, %3, implicit-def $vcc, implicit $exec
375 %6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec
377 %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
378 %8:vgpr_32 = V_ADD_I32_e32 %7, %1, implicit-def $vcc, implicit $exec
379 ; this breaks the sequence
380 %9:vgpr_32 = V_SUB_I32_e32 5, %7, implicit-def $vcc, implicit $exec
383 # tests on sequences of dpp consumers followed by control flow
384 # GCN-LABEL: name: dpp_seq_cf
385 # GCN: %4:vgpr_32 = V_ADD_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
386 # GCN: %5:vgpr_32 = V_SUBREV_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
387 # GCN: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
390 tracksRegLiveness: true
393 successors: %bb.1, %bb.2
394 liveins: $vgpr0, $vgpr1
395 %0:vgpr_32 = COPY $vgpr0
396 %1:vgpr_32 = COPY $vgpr1
397 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
399 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
400 %4:vgpr_32 = V_ADD_I32_e32 %3, %1, implicit-def $vcc, implicit $exec
401 %5:vgpr_32 = V_SUB_I32_e32 %1, %3, implicit-def $vcc, implicit $exec
402 %6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec
404 %7:sreg_64 = V_CMP_EQ_U32_e64 %5, %6, implicit $exec
405 %8:sreg_64 = SI_IF %7, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
412 SI_END_CF %8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
415 # old reg def is in diff BB - cannot combine
416 # GCN-LABEL: name: old_in_diff_bb
417 # GCN: %3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec
420 tracksRegLiveness: true
424 liveins: $vgpr0, $vgpr1
426 %0:vgpr_32 = COPY $vgpr0
427 %1:vgpr_32 = COPY $vgpr1
428 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
432 %3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec
433 %4:vgpr_32 = V_ADD_U32_e32 %3, %0, implicit $exec
436 # old reg def is in diff BB but bound_ctrl:0 - can combine
437 # GCN-LABEL: name: old_in_diff_bb_bctrl_zero
438 # GCN: %4:vgpr_32 = V_ADD_U32_dpp {{%[0-9]}}, %0, %1, 1, 15, 15, 1, implicit $exec
440 name: old_in_diff_bb_bctrl_zero
441 tracksRegLiveness: true
445 liveins: $vgpr0, $vgpr1
447 %0:vgpr_32 = COPY $vgpr0
448 %1:vgpr_32 = COPY $vgpr1
449 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
453 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
454 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
457 # EXEC mask changed between def and use - cannot combine
458 # GCN-LABEL: name: exec_changed
459 # GCN: %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
462 tracksRegLiveness: true
465 liveins: $vgpr0, $vgpr1
467 %0:vgpr_32 = COPY $vgpr0
468 %1:vgpr_32 = COPY $vgpr1
469 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
470 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
471 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
472 %5:sreg_64 = COPY $exec, implicit-def $exec
473 %6:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
476 # test if $old definition is correctly tracked through subreg manipulation pseudos
478 # GCN-LABEL: name: mul_old_subreg
479 # GCN: %7:vgpr_32 = V_MUL_I32_I24_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
482 tracksRegLiveness: true
485 liveins: $vgpr0, $vgpr1
487 %0:vreg_64 = COPY $vgpr0
488 %1:vgpr_32 = COPY $vgpr1
489 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
490 %3:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
491 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
492 %5:vreg_64 = INSERT_SUBREG %4, %1, %subreg.sub1 ; %5.sub0 is taken from %4
493 %6:vgpr_32 = V_MOV_B32_dpp %5.sub0, %1, 1, 1, 1, 0, implicit $exec
494 %7:vgpr_32 = V_MUL_I32_I24_e32 %6, %0.sub1, implicit $exec
497 # GCN-LABEL: name: add_old_subreg
498 # GCN: %5:vgpr_32 = V_ADD_U32_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
501 tracksRegLiveness: true
504 liveins: $vgpr0, $vgpr1
506 %0:vreg_64 = COPY $vgpr0
507 %1:vgpr_32 = COPY $vgpr1
508 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
509 %3:vreg_64 = INSERT_SUBREG %0, %2, %subreg.sub1 ; %3.sub1 is inserted
510 %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 1, 1, 0, implicit $exec
511 %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
514 # GCN-LABEL: name: add_old_subreg_undef
515 # GCN: %5:vgpr_32 = V_ADD_U32_dpp undef %3.sub1, %1, %0.sub1, 1, 15, 15, 1, implicit $exec
517 name: add_old_subreg_undef
518 tracksRegLiveness: true
521 liveins: $vgpr0, $vgpr1
523 %0:vreg_64 = COPY $vgpr0
524 %1:vgpr_32 = COPY $vgpr1
525 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
526 %3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef
527 %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 15, 15, 1, implicit $exec
528 %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
531 # Test instruction which does not have modifiers in VOP1 form but does in DPP form.
532 # GCN-LABEL: name: dpp_vop1
533 # GCN: %3:vgpr_32 = V_CEIL_F32_dpp %0, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $exec
535 tracksRegLiveness: true
538 %1:vgpr_32 = IMPLICIT_DEF
539 %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
540 %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $exec
543 # Test instruction which does not have modifiers in VOP2 form but does in DPP form.
544 # GCN-LABEL: name: dpp_min
545 # GCN: %3:vgpr_32 = V_MIN_F32_dpp %0, 0, undef %2:vgpr_32, 0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $exec
547 tracksRegLiveness: true
550 %1:vgpr_32 = IMPLICIT_DEF
551 %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
552 %4:vgpr_32 = V_MIN_F32_e32 %2, undef %3:vgpr_32, implicit $exec
555 # Test an undef old operand
556 # GCN-LABEL: name: dpp_undef_old
557 # GCN: %3:vgpr_32 = V_CEIL_F32_dpp undef %1:vgpr_32, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $exec
559 tracksRegLiveness: true
562 %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
563 %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $exec
566 # Do not combine a dpp mov which writes a physreg.
567 # GCN-LABEL: name: phys_dpp_mov_dst
568 # GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
569 # GCN: %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $exec
570 name: phys_dpp_mov_dst
571 tracksRegLiveness: true
574 $vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
575 %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $exec
578 # Do not combine a dpp mov which reads a physreg.
579 # GCN-LABEL: name: phys_dpp_mov_old_src
580 # GCN: %0:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
581 # GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $exec
582 name: phys_dpp_mov_old_src
583 tracksRegLiveness: true
586 %1:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
587 %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $exec
590 # Do not combine a dpp mov which reads a physreg.
591 # GCN-LABEL: name: phys_dpp_mov_src
592 # GCN: %0:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec
593 # GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $exec
594 name: phys_dpp_mov_src
595 tracksRegLiveness: true
598 %1:vgpr_32 = V_MOV_B32_dpp undef %0:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec
599 %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $exec
602 # GCN-LABEL: name: dpp_reg_sequence_both_combined
603 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
604 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
605 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
606 # GCN: %9:vgpr_32 = IMPLICIT_DEF
607 # GCN: %8:vgpr_32 = IMPLICIT_DEF
608 # GCN: %6:vgpr_32 = V_ADD_I32_dpp %9, %1.sub0, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
609 # GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
610 name: dpp_reg_sequence_both_combined
611 tracksRegLiveness: true
614 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
616 %0:vreg_64 = COPY $vgpr0_vgpr1
617 %1:vreg_64 = COPY $vgpr2_vgpr3
618 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
619 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
620 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
621 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
622 %6:vgpr_32 = V_ADD_I32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
623 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
626 # GCN-LABEL: name: dpp_reg_sequence_first_combined
627 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
628 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
629 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
630 # GCN: %8:vgpr_32 = IMPLICIT_DEF
631 # GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
632 # GCN: %5:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, %4, %subreg.sub1
633 # GCN: %6:vgpr_32 = V_ADD_I32_dpp %8, %1.sub0, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
634 # GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
635 name: dpp_reg_sequence_first_combined
636 tracksRegLiveness: true
639 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
641 %0:vreg_64 = COPY $vgpr0_vgpr1
642 %1:vreg_64 = COPY $vgpr2_vgpr3
643 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
644 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
645 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
646 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
647 %6:vgpr_32 = V_ADD_I32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
648 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
651 # GCN-LABEL: name: dpp_reg_sequence_second_combined
652 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
653 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
654 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
655 # GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
656 # GCN: %8:vgpr_32 = IMPLICIT_DEF
657 # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, undef %4:vgpr_32, %subreg.sub1
658 # GCN: %6:vgpr_32 = V_ADD_I32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec
659 # GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
660 name: dpp_reg_sequence_second_combined
661 tracksRegLiveness: true
664 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
666 %0:vreg_64 = COPY $vgpr0_vgpr1
667 %1:vreg_64 = COPY $vgpr2_vgpr3
668 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
669 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
670 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
671 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
672 %6:vgpr_32 = V_ADD_I32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
673 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
676 # GCN-LABEL: name: dpp_reg_sequence_none_combined
677 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
678 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
679 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
680 # GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
681 # GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
682 # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
683 # GCN: %6:vgpr_32 = V_ADD_I32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec
684 # GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
685 name: dpp_reg_sequence_none_combined
686 tracksRegLiveness: true
689 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
691 %0:vreg_64 = COPY $vgpr0_vgpr1
692 %1:vreg_64 = COPY $vgpr2_vgpr3
693 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
694 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
695 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
696 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
697 %6:vgpr_32 = V_ADD_I32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
698 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
701 # GCN-LABEL: name: dpp_reg_sequence_exec_changed
702 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
703 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
704 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
705 # GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
706 # GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
707 # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
708 # GCN: S_BRANCH %bb.1
710 # GCN: %6:vgpr_32 = V_ADD_I32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec
711 # GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
712 name: dpp_reg_sequence_exec_changed
713 tracksRegLiveness: true
716 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
718 %0:vreg_64 = COPY $vgpr0_vgpr1
719 %1:vreg_64 = COPY $vgpr2_vgpr3
720 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
721 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
722 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
723 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
727 %6:vgpr_32 = V_ADD_I32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
728 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
731 # GCN-LABEL: name: dpp_reg_sequence_subreg
732 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
733 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
734 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
735 # GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
736 # GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
737 # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
738 # GCN: %6:vreg_64 = REG_SEQUENCE %5.sub0, %subreg.sub0, %5.sub1, %subreg.sub1
739 # GCN: %7:vgpr_32 = V_ADD_I32_e32 %6.sub0, %2, implicit-def $vcc, implicit $exec
740 # GCN: %8:vgpr_32 = V_ADDC_U32_e32 %6.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
741 name: dpp_reg_sequence_subreg
742 tracksRegLiveness: true
745 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
747 %0:vreg_64 = COPY $vgpr0_vgpr1
748 %1:vreg_64 = COPY $vgpr2_vgpr3
749 %8:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
750 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
751 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
752 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
753 %5:vreg_64 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub1, %subreg.sub1
754 %6:vgpr_32 = V_ADD_I32_e32 %5.sub0, %8, implicit-def $vcc, implicit $exec
755 %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %8, implicit-def $vcc, implicit $vcc, implicit $exec
758 # GCN-LABEL: name: dpp64_add64_impdef
759 # GCN: %3:vgpr_32 = V_ADD_I32_dpp %1.sub0, %0.sub0, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
760 # GCN: %5:vgpr_32 = V_ADDC_U32_dpp %1.sub1, %0.sub1, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
761 name: dpp64_add64_impdef
762 tracksRegLiveness: true
765 %0:vreg_64 = IMPLICIT_DEF
766 %1:vreg_64 = IMPLICIT_DEF
767 %2:vreg_64 = V_MOV_B64_DPP_PSEUDO %1:vreg_64, %0:vreg_64, 1, 15, 15, 1, implicit $exec
768 %5:vgpr_32 = V_ADD_I32_e32 %2.sub0, undef %4:vgpr_32, implicit-def $vcc, implicit $exec
769 %6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec
772 # GCN-LABEL: name: dpp64_add64_undef
773 # GCN: %3:vgpr_32 = V_ADD_I32_dpp undef %1.sub0:vreg_64, undef %2.sub0:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
774 # GCN: %5:vgpr_32 = V_ADDC_U32_dpp undef %1.sub1:vreg_64, undef %2.sub1:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
775 name: dpp64_add64_undef
776 tracksRegLiveness: true
779 %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec
780 %5:vgpr_32 = V_ADD_I32_e32 %2.sub0, undef %4:vgpr_32, implicit-def $vcc, implicit $exec
781 %6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec
784 # GCN-LABEL: name: dpp64_add64_first_combined
785 # GCN: %8:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64, undef %2.sub1:vreg_64, 1, 15, 15, 1, implicit $exec
786 # GCN: %0:vreg_64 = REG_SEQUENCE undef %7:vgpr_32, %subreg.sub0, %8, %subreg.sub1
787 # GCN: %3:vgpr_32 = V_ADD_I32_dpp undef %1.sub0:vreg_64, undef %2.sub0:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
788 # GCN: %5:vgpr_32, dead %6:sreg_64_xexec = V_ADDC_U32_e64 1, %0.sub1, undef $vcc, 0, implicit $exec
789 name: dpp64_add64_first_combined
790 tracksRegLiveness: true
793 %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec
794 %4:vgpr_32 = V_ADD_I32_e32 %2.sub0, undef %3:vgpr_32, implicit-def $vcc, implicit $exec
795 %5:vgpr_32, dead %6:sreg_64_xexec = V_ADDC_U32_e64 1, %2.sub1, undef $vcc, 0, implicit $exec