1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
4 ; CHECK-LABEL: {{^}}else_no_execfix:
6 ; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
7 ; CHECK-NEXT: s_xor_b64 exec, exec, [[DST]]
8 ; CHECK-NEXT: ; mask branch
9 define amdgpu_ps float @else_no_execfix(i32 %z, float %v) #0 {
11 %cc = icmp sgt i32 %z, 5
12 br i1 %cc, label %if, label %else
15 %v.if = fmul float %v, 2.0
19 %v.else = fmul float %v, 3.0
23 %r = phi float [ %v.if, %if ], [ %v.else, %else ]
27 ; CHECK-LABEL: {{^}}else_execfix_leave_wqm:
29 ; CHECK-NEXT: s_mov_b64 [[INIT_EXEC:s\[[0-9]+:[0-9]+\]]], exec
31 ; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
32 ; CHECK-NEXT: s_and_b64 exec, exec, [[INIT_EXEC]]
33 ; CHECK-NEXT: s_and_b64 [[AND_INIT:s\[[0-9]+:[0-9]+\]]], exec, [[DST]]
34 ; CHECK-NEXT: s_xor_b64 exec, exec, [[AND_INIT]]
35 ; CHECK-NEXT: ; mask branch
36 define amdgpu_ps void @else_execfix_leave_wqm(i32 %z, float %v) #0 {
38 %cc = icmp sgt i32 %z, 5
39 br i1 %cc, label %if, label %else
42 %v.if = fmul float %v, 2.0
46 %c = fmul float %v, 3.0
47 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
48 %v.else = extractelement <4 x float> %tex, i32 0
52 %r = phi float [ %v.if, %if ], [ %v.else, %else ]
53 call void @llvm.amdgcn.buffer.store.f32(float %r, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
57 declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1
58 declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
60 attributes #0 = { nounwind }
61 attributes #1 = { nounwind writeonly }
62 attributes #2 = { nounwind readonly }