1 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=CIVI %s
2 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GFX89 -check-prefix=GCN -check-prefix=CIVI %s
3 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX89 -check-prefix=GFX9 -check-prefix=GCN %s
5 ; GCN-LABEL: {{^}}fneg_fabs_fadd_f16:
6 ; CI-DAG: v_cvt_f32_f16_e32
7 ; CI-DAG: v_cvt_f32_f16_e64 [[CVT_ABS_X:v[0-9]+]], |s{{[0-9]+}}|
8 ; CI: v_sub_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[CVT_ABS_X]]
11 ; GFX89: v_sub_f16_e64 {{v[0-9]+}}, {{s[0-9]+}}, |{{v[0-9]+}}|
12 define amdgpu_kernel void @fneg_fabs_fadd_f16(half addrspace(1)* %out, half %x, half %y) {
13 %fabs = call half @llvm.fabs.f16(half %x)
14 %fsub = fsub half -0.0, %fabs
15 %fadd = fadd half %y, %fsub
16 store half %fadd, half addrspace(1)* %out, align 2
20 ; GCN-LABEL: {{^}}fneg_fabs_fmul_f16:
21 ; CI-DAG: v_cvt_f32_f16_e32
22 ; CI-DAG: v_cvt_f32_f16_e64 [[CVT_NEG_ABS_X:v[0-9]+]], -|{{s[0-9]+}}|
23 ; CI: v_mul_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, [[CVT_NEG_ABS_X]]
24 ; CI: v_cvt_f16_f32_e32
27 ; GFX89: v_mul_f16_e64 [[MUL:v[0-9]+]], {{s[0-9]+}}, -|{{v[0-9]+}}|
29 ; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
30 define amdgpu_kernel void @fneg_fabs_fmul_f16(half addrspace(1)* %out, half %x, half %y) {
31 %fabs = call half @llvm.fabs.f16(half %x)
32 %fsub = fsub half -0.0, %fabs
33 %fmul = fmul half %y, %fsub
34 store half %fmul, half addrspace(1)* %out, align 2
38 ; DAGCombiner will transform:
39 ; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF))
40 ; unless isFabsFree returns true
42 ; GCN-LABEL: {{^}}fneg_fabs_free_f16:
43 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000
44 define amdgpu_kernel void @fneg_fabs_free_f16(half addrspace(1)* %out, i16 %in) {
45 %bc = bitcast i16 %in to half
46 %fabs = call half @llvm.fabs.f16(half %bc)
47 %fsub = fsub half -0.0, %fabs
48 store half %fsub, half addrspace(1)* %out
52 ; GCN-LABEL: {{^}}fneg_fabs_f16:
53 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000
54 define amdgpu_kernel void @fneg_fabs_f16(half addrspace(1)* %out, half %in) {
55 %fabs = call half @llvm.fabs.f16(half %in)
56 %fsub = fsub half -0.0, %fabs
57 store half %fsub, half addrspace(1)* %out, align 2
61 ; GCN-LABEL: {{^}}v_fneg_fabs_f16:
62 ; GCN: v_or_b32_e32 v{{[0-9]+}}, 0x8000, v{{[0-9]+}}
63 define amdgpu_kernel void @v_fneg_fabs_f16(half addrspace(1)* %out, half addrspace(1)* %in) {
64 %val = load half, half addrspace(1)* %in, align 2
65 %fabs = call half @llvm.fabs.f16(half %val)
66 %fsub = fsub half -0.0, %fabs
67 store half %fsub, half addrspace(1)* %out, align 2
71 ; GCN-LABEL: {{^}}s_fneg_fabs_v2f16_non_bc_src:
72 ; GFX9-DAG: s_load_dword [[VAL:s[0-9]+]]
73 ; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x40003c00
74 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[VAL]], [[K]]
75 ; GFX9: v_or_b32_e32 [[RESULT:v[0-9]+]], 0x80008000, [[ADD]]
77 ; VI: v_or_b32_e32 v{{[0-9]+}}, 0x80008000, v{{[0-9]+}}
78 define amdgpu_kernel void @s_fneg_fabs_v2f16_non_bc_src(<2 x half> addrspace(1)* %out, <2 x half> %in) {
79 %add = fadd <2 x half> %in, <half 1.0, half 2.0>
80 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %add)
81 %fneg.fabs = fsub <2 x half> <half -0.0, half -0.0>, %fabs
82 store <2 x half> %fneg.fabs, <2 x half> addrspace(1)* %out
86 ; FIXME: single bit op
88 ; Combine turns this into integer op when bitcast source (from load)
90 ; GCN-LABEL: {{^}}s_fneg_fabs_v2f16_bc_src:
91 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008000
92 define amdgpu_kernel void @s_fneg_fabs_v2f16_bc_src(<2 x half> addrspace(1)* %out, <2 x half> %in) {
93 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
94 %fneg.fabs = fsub <2 x half> <half -0.0, half -0.0>, %fabs
95 store <2 x half> %fneg.fabs, <2 x half> addrspace(1)* %out
99 ; GCN-LABEL: {{^}}fneg_fabs_v4f16:
100 ; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0x80008000
101 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[MASK]]
102 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[MASK]]
103 ; GCN: {{flat|global}}_store_dwordx2
104 define amdgpu_kernel void @fneg_fabs_v4f16(<4 x half> addrspace(1)* %out, <4 x half> %in) {
105 %fabs = call <4 x half> @llvm.fabs.v4f16(<4 x half> %in)
106 %fsub = fsub <4 x half> <half -0.0, half -0.0, half -0.0, half -0.0>, %fabs
107 store <4 x half> %fsub, <4 x half> addrspace(1)* %out
111 ; GCN-LABEL: {{^}}fold_user_fneg_fabs_v2f16:
112 ; CI: s_load_dword [[IN:s[0-9]+]]
114 ; CI: v_cvt_f32_f16_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
115 ; CI: v_cvt_f32_f16_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
116 ; CI: v_mul_f32_e32 v{{[0-9]+}}, -4.0, v{{[0-9]+}}
117 ; CI: v_mul_f32_e32 v{{[0-9]+}}, -4.0, v{{[0-9]+}}
119 ; VI: v_mul_f16_e64 v{{[0-9]+}}, |s{{[0-9]+}}|, -4.0
120 ; VI: v_mul_f16_sdwa v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
122 ; GFX9: s_and_b32 [[ABS:s[0-9]+]], s{{[0-9]+}}, 0x7fff7fff
123 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, [[ABS]], -4.0 op_sel_hi:[1,0]
124 define amdgpu_kernel void @fold_user_fneg_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) #0 {
125 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
126 %fneg.fabs = fsub <2 x half> <half -0.0, half -0.0>, %fabs
127 %mul = fmul <2 x half> %fneg.fabs, <half 4.0, half 4.0>
128 store <2 x half> %mul, <2 x half> addrspace(1)* %out
132 ; GCN-LABEL: {{^}}s_fneg_multi_use_fabs_v2f16:
133 ; GFX9: s_and_b32 [[ABS:s[0-9]+]], s{{[0-9]+}}, 0x7fff7fff
134 ; GFX9: v_mov_b32_e32 [[V_ABS:v[0-9]+]], [[ABS]]
135 ; GFX9: s_xor_b32 [[NEG:s[0-9]+]], [[ABS]], 0x80008000
136 ; GFX9-DAG: v_mov_b32_e32 [[V_NEG:v[0-9]+]], [[NEG]]
137 ; GFX9-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[V_ABS]]
138 ; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[V_NEG]]
139 define amdgpu_kernel void @s_fneg_multi_use_fabs_v2f16(<2 x half> addrspace(1)* %out0, <2 x half> addrspace(1)* %out1, <2 x half> %in) {
140 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
141 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %fabs
142 store <2 x half> %fabs, <2 x half> addrspace(1)* %out0
143 store <2 x half> %fneg, <2 x half> addrspace(1)* %out1
147 ; GCN-LABEL: {{^}}s_fneg_multi_use_fabs_foldable_neg_v2f16:
148 ; GFX9: s_and_b32 [[ABS:s[0-9]+]], s{{[0-9]+}}, 0x7fff7fff
149 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, [[ABS]], -4.0 op_sel_hi:[1,0]
150 define amdgpu_kernel void @s_fneg_multi_use_fabs_foldable_neg_v2f16(<2 x half> addrspace(1)* %out0, <2 x half> addrspace(1)* %out1, <2 x half> %in) {
151 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
152 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %fabs
153 %mul = fmul <2 x half> %fneg, <half 4.0, half 4.0>
154 store <2 x half> %fabs, <2 x half> addrspace(1)* %out0
155 store <2 x half> %mul, <2 x half> addrspace(1)* %out1
159 declare half @llvm.fabs.f16(half) #1
160 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #1
161 declare <4 x half> @llvm.fabs.v4f16(<4 x half>) #1
163 attributes #0 = { nounwind }
164 attributes #1 = { nounwind readnone }