1 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
3 ; GCN-LABEL: {{^}}load_1d:
4 ; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16
5 define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
7 %s = extractelement <2 x i16> %coords, i32 0
8 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
12 ; GCN-LABEL: {{^}}load_2d:
13 ; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16
14 define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
16 %s = extractelement <2 x i16> %coords, i32 0
17 %t = extractelement <2 x i16> %coords, i32 1
18 %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
22 ; GCN-LABEL: {{^}}load_3d:
23 ; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
24 define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
26 %s = extractelement <2 x i16> %coords_lo, i32 0
27 %t = extractelement <2 x i16> %coords_lo, i32 1
28 %r = extractelement <2 x i16> %coords_hi, i32 0
29 %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
33 ; GCN-LABEL: {{^}}load_cube:
34 ; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
35 define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
37 %s = extractelement <2 x i16> %coords_lo, i32 0
38 %t = extractelement <2 x i16> %coords_lo, i32 1
39 %slice = extractelement <2 x i16> %coords_hi, i32 0
40 %v = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
44 ; GCN-LABEL: {{^}}load_1darray:
45 ; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}
46 define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
48 %s = extractelement <2 x i16> %coords, i32 0
49 %slice = extractelement <2 x i16> %coords, i32 1
50 %v = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i16(i32 15, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
54 ; GCN-LABEL: {{^}}load_2darray:
55 ; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
56 define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
58 %s = extractelement <2 x i16> %coords_lo, i32 0
59 %t = extractelement <2 x i16> %coords_lo, i32 1
60 %slice = extractelement <2 x i16> %coords_hi, i32 0
61 %v = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
65 ; GCN-LABEL: {{^}}load_2dmsaa:
66 ; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
67 define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
69 %s = extractelement <2 x i16> %coords_lo, i32 0
70 %t = extractelement <2 x i16> %coords_lo, i32 1
71 %fragid = extractelement <2 x i16> %coords_hi, i32 0
72 %v = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
76 ; GCN-LABEL: {{^}}load_2darraymsaa:
77 ; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
78 define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
80 %s = extractelement <2 x i16> %coords_lo, i32 0
81 %t = extractelement <2 x i16> %coords_lo, i32 1
82 %slice = extractelement <2 x i16> %coords_hi, i32 0
83 %fragid = extractelement <2 x i16> %coords_hi, i32 1
84 %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
88 ; GCN-LABEL: {{^}}load_mip_1d:
89 ; GCN: image_load_mip v[0:3], v0, s[0:7] dmask:0xf unorm a16
90 define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
92 %s = extractelement <2 x i16> %coords, i32 0
93 %mip = extractelement <2 x i16> %coords, i32 1
94 %v = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i16(i32 15, i16 %s, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
98 ; GCN-LABEL: {{^}}load_mip_2d:
99 ; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
100 define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
102 %s = extractelement <2 x i16> %coords_lo, i32 0
103 %t = extractelement <2 x i16> %coords_lo, i32 1
104 %mip = extractelement <2 x i16> %coords_hi, i32 0
105 %v = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
109 ; GCN-LABEL: {{^}}load_mip_3d:
110 ; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
111 define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
113 %s = extractelement <2 x i16> %coords_lo, i32 0
114 %t = extractelement <2 x i16> %coords_lo, i32 1
115 %r = extractelement <2 x i16> %coords_hi, i32 0
116 %mip = extractelement <2 x i16> %coords_hi, i32 1
117 %v = call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
121 ; GCN-LABEL: {{^}}load_mip_cube:
122 ; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
123 define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
125 %s = extractelement <2 x i16> %coords_lo, i32 0
126 %t = extractelement <2 x i16> %coords_lo, i32 1
127 %slice = extractelement <2 x i16> %coords_hi, i32 0
128 %mip = extractelement <2 x i16> %coords_hi, i32 1
129 %v = call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
133 ; GCN-LABEL: {{^}}load_mip_1darray:
134 ; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
135 define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
137 %s = extractelement <2 x i16> %coords_lo, i32 0
138 %slice = extractelement <2 x i16> %coords_lo, i32 1
139 %mip = extractelement <2 x i16> %coords_hi, i32 0
140 %v = call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i16(i32 15, i16 %s, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
144 ; GCN-LABEL: {{^}}load_mip_2darray:
145 ; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
146 define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
148 %s = extractelement <2 x i16> %coords_lo, i32 0
149 %t = extractelement <2 x i16> %coords_lo, i32 1
150 %slice = extractelement <2 x i16> %coords_hi, i32 0
151 %mip = extractelement <2 x i16> %coords_hi, i32 1
152 %v = call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
156 ; GCN-LABEL: {{^}}store_1d:
157 ; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16
158 define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
160 %s = extractelement <2 x i16> %coords, i32 0
161 call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
165 ; GCN-LABEL: {{^}}store_2d:
166 ; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16
167 define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
169 %s = extractelement <2 x i16> %coords, i32 0
170 %t = extractelement <2 x i16> %coords, i32 1
171 call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
175 ; GCN-LABEL: {{^}}store_3d:
176 ; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16
177 define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
179 %s = extractelement <2 x i16> %coords_lo, i32 0
180 %t = extractelement <2 x i16> %coords_lo, i32 1
181 %r = extractelement <2 x i16> %coords_hi, i32 0
182 call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
186 ; GCN-LABEL: {{^}}store_cube:
187 ; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
188 define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
190 %s = extractelement <2 x i16> %coords_lo, i32 0
191 %t = extractelement <2 x i16> %coords_lo, i32 1
192 %slice = extractelement <2 x i16> %coords_hi, i32 0
193 call void @llvm.amdgcn.image.store.cube.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
197 ; GCN-LABEL: {{^}}store_1darray:
198 ; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16 da{{$}}
199 define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
201 %s = extractelement <2 x i16> %coords, i32 0
202 %slice = extractelement <2 x i16> %coords, i32 1
203 call void @llvm.amdgcn.image.store.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
207 ; GCN-LABEL: {{^}}store_2darray:
208 ; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
209 define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
211 %s = extractelement <2 x i16> %coords_lo, i32 0
212 %t = extractelement <2 x i16> %coords_lo, i32 1
213 %slice = extractelement <2 x i16> %coords_hi, i32 0
214 call void @llvm.amdgcn.image.store.2darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
218 ; GCN-LABEL: {{^}}store_2dmsaa:
219 ; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16
220 define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
222 %s = extractelement <2 x i16> %coords_lo, i32 0
223 %t = extractelement <2 x i16> %coords_lo, i32 1
224 %fragid = extractelement <2 x i16> %coords_hi, i32 0
225 call void @llvm.amdgcn.image.store.2dmsaa.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
229 ; GCN-LABEL: {{^}}store_2darraymsaa:
230 ; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
231 define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
233 %s = extractelement <2 x i16> %coords_lo, i32 0
234 %t = extractelement <2 x i16> %coords_lo, i32 1
235 %slice = extractelement <2 x i16> %coords_hi, i32 0
236 %fragid = extractelement <2 x i16> %coords_hi, i32 1
237 call void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
241 ; GCN-LABEL: {{^}}store_mip_1d:
242 ; GCN: image_store_mip v[0:3], v4, s[0:7] dmask:0xf unorm a16
243 define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
245 %s = extractelement <2 x i16> %coords, i32 0
246 %mip = extractelement <2 x i16> %coords, i32 1
247 call void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
251 ; GCN-LABEL: {{^}}store_mip_2d:
252 ; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16
253 define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
255 %s = extractelement <2 x i16> %coords_lo, i32 0
256 %t = extractelement <2 x i16> %coords_lo, i32 1
257 %mip = extractelement <2 x i16> %coords_hi, i32 0
258 call void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
262 ; GCN-LABEL: {{^}}store_mip_3d:
263 ; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16
264 define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
266 %s = extractelement <2 x i16> %coords_lo, i32 0
267 %t = extractelement <2 x i16> %coords_lo, i32 1
268 %r = extractelement <2 x i16> %coords_hi, i32 0
269 %mip = extractelement <2 x i16> %coords_hi, i32 1
270 call void @llvm.amdgcn.image.store.mip.3d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %r, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
274 ; GCN-LABEL: {{^}}store_mip_cube:
275 ; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
276 define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
278 %s = extractelement <2 x i16> %coords_lo, i32 0
279 %t = extractelement <2 x i16> %coords_lo, i32 1
280 %slice = extractelement <2 x i16> %coords_hi, i32 0
281 %mip = extractelement <2 x i16> %coords_hi, i32 1
282 call void @llvm.amdgcn.image.store.mip.cube.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
286 ; GCN-LABEL: {{^}}store_mip_1darray:
287 ; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
288 define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
290 %s = extractelement <2 x i16> %coords_lo, i32 0
291 %slice = extractelement <2 x i16> %coords_lo, i32 1
292 %mip = extractelement <2 x i16> %coords_hi, i32 0
293 call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
297 ; GCN-LABEL: {{^}}store_mip_2darray:
298 ; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
299 define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
301 %s = extractelement <2 x i16> %coords_lo, i32 0
302 %t = extractelement <2 x i16> %coords_lo, i32 1
303 %slice = extractelement <2 x i16> %coords_hi, i32 0
304 %mip = extractelement <2 x i16> %coords_hi, i32 1
305 call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
309 ; GCN-LABEL: {{^}}getresinfo_1d:
310 ; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16
311 define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
313 %mip = extractelement <2 x i16> %coords, i32 0
314 %v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
318 ; GCN-LABEL: {{^}}getresinfo_2d:
319 ; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16
320 define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
322 %mip = extractelement <2 x i16> %coords, i32 0
323 %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
327 ; GCN-LABEL: {{^}}getresinfo_3d:
328 ; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16
329 define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
331 %mip = extractelement <2 x i16> %coords, i32 0
332 %v = call <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
336 ; GCN-LABEL: {{^}}getresinfo_cube:
337 ; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}
338 define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
340 %mip = extractelement <2 x i16> %coords, i32 0
341 %v = call <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
345 ; GCN-LABEL: {{^}}getresinfo_1darray:
346 ; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}
347 define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
349 %mip = extractelement <2 x i16> %coords, i32 0
350 %v = call <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
354 ; GCN-LABEL: {{^}}getresinfo_2darray:
355 ; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}
356 define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
358 %mip = extractelement <2 x i16> %coords, i32 0
359 %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
363 ; GCN-LABEL: {{^}}getresinfo_2dmsaa:
364 ; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16
365 define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
367 %mip = extractelement <2 x i16> %coords, i32 0
368 %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
372 ; GCN-LABEL: {{^}}getresinfo_2darraymsaa:
373 ; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}
374 define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
376 %mip = extractelement <2 x i16> %coords, i32 0
377 %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
381 ; GCN-LABEL: {{^}}load_1d_V1:
382 ; GCN: image_load v0, v0, s[0:7] dmask:0x8 unorm a16
383 define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
385 %s = extractelement <2 x i16> %coords, i32 0
386 %v = call float @llvm.amdgcn.image.load.1d.f32.i16(i32 8, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
390 ; GCN-LABEL: {{^}}load_1d_V2:
391 ; GCN: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm a16
392 define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
394 %s = extractelement <2 x i16> %coords, i32 0
395 %v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32 9, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
399 ; GCN-LABEL: {{^}}store_1d_V1:
400 ; GCN: image_store v0, v1, s[0:7] dmask:0x2 unorm a16
401 define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16> %coords) {
403 %s = extractelement <2 x i16> %coords, i32 0
404 call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
408 ; GCN-LABEL: {{^}}store_1d_V2:
409 ; GCN: image_store v[0:1], v2, s[0:7] dmask:0xc unorm a16
410 define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2 x i16> %coords) {
412 %s = extractelement <2 x i16> %coords, i32 0
413 call void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float> %vdata, i32 12, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
417 ; GCN-LABEL: {{^}}load_1d_glc:
418 ; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc a16{{$}}
419 define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
421 %s = extractelement <2 x i16> %coords, i32 0
422 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
426 ; GCN-LABEL: {{^}}load_1d_slc:
427 ; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm slc a16{{$}}
428 define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
430 %s = extractelement <2 x i16> %coords, i32 0
431 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
435 ; GCN-LABEL: {{^}}load_1d_glc_slc:
436 ; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc slc a16{{$}}
437 define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
439 %s = extractelement <2 x i16> %coords, i32 0
440 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
444 ; GCN-LABEL: {{^}}store_1d_glc:
445 ; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc a16{{$}}
446 define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
448 %s = extractelement <2 x i16> %coords, i32 0
449 call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
453 ; GCN-LABEL: {{^}}store_1d_slc:
454 ; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm slc a16{{$}}
455 define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
457 %s = extractelement <2 x i16> %coords, i32 0
458 call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
462 ; GCN-LABEL: {{^}}store_1d_glc_slc:
463 ; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc slc a16{{$}}
464 define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
466 %s = extractelement <2 x i16> %coords, i32 0
467 call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
471 ; GCN-LABEL: {{^}}getresinfo_dmask0:
473 ; GCN: ; return to shader part epilog
474 define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) #0 {
476 %mip = extractelement <2 x i16> %coords, i32 0
477 %r = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 0, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
481 declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #1
482 declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
483 declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
484 declare <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
485 declare <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
486 declare <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
487 declare <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
488 declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
490 declare <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
491 declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
492 declare <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
493 declare <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
494 declare <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
495 declare <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
497 declare void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float>, i32, i16, <8 x i32>, i32, i32) #0
498 declare void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0
499 declare void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
500 declare void @llvm.amdgcn.image.store.cube.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
501 declare void @llvm.amdgcn.image.store.1darray.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0
502 declare void @llvm.amdgcn.image.store.2darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
503 declare void @llvm.amdgcn.image.store.2dmsaa.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
504 declare void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
506 declare void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0
507 declare void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
508 declare void @llvm.amdgcn.image.store.mip.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
509 declare void @llvm.amdgcn.image.store.mip.cube.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
510 declare void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
511 declare void @llvm.amdgcn.image.store.mip.2darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
513 declare <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
514 declare <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
515 declare <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
516 declare <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
517 declare <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
518 declare <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
519 declare <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
520 declare <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
522 declare float @llvm.amdgcn.image.load.1d.f32.i16(i32, i16, <8 x i32>, i32, i32) #1
523 declare float @llvm.amdgcn.image.load.2d.f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
524 declare <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32, i16, <8 x i32>, i32, i32) #1
525 declare void @llvm.amdgcn.image.store.1d.f32.i16(float, i32, i16, <8 x i32>, i32, i32) #0
526 declare void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float>, i32, i16, <8 x i32>, i32, i32) #0
528 attributes #0 = { nounwind }
529 attributes #1 = { nounwind readonly }
530 attributes #2 = { nounwind readnone }