1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
4 ; GCN-LABEL: {{^}}is_private_vgpr:
5 ; GCN-DAG: {{flat|global}}_load_dwordx2 v{{\[[0-9]+}}:[[PTR_HI:[0-9]+]]{{\]}}
6 ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11
7 ; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16)
8 ; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16
9 ; GCN: v_cmp_eq_u32_e32 vcc, [[APERTURE]], v[[PTR_HI]]
10 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
11 define amdgpu_kernel void @is_private_vgpr(i8* addrspace(1)* %ptr.ptr) {
12 %id = call i32 @llvm.amdgcn.workitem.id.x()
13 %gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id
14 %ptr = load volatile i8*, i8* addrspace(1)* %gep
15 %val = call i1 @llvm.amdgcn.is.private(i8* %ptr)
16 %ext = zext i1 %val to i32
17 store i32 %ext, i32 addrspace(1)* undef
21 ; FIXME: setcc (zero_extend (setcc)), 1) not folded out, resulting in
22 ; select and vcc branch.
24 ; GCN-LABEL: {{^}}is_private_sgpr:
25 ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}}
26 ; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16)
28 ; CI-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x1{{$}}
29 ; GFX9-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x4{{$}}
30 ; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16
32 ; GCN: v_mov_b32_e32 [[V_APERTURE:v[0-9]+]], [[APERTURE]]
33 ; GCN: v_cmp_eq_u32_e32 vcc, [[PTR_HI]], [[V_APERTURE]]
34 ; GCN: s_cbranch_vccnz
35 define amdgpu_kernel void @is_private_sgpr(i8* %ptr) {
36 %val = call i1 @llvm.amdgcn.is.private(i8* %ptr)
37 br i1 %val, label %bb0, label %bb1
40 store volatile i32 0, i32 addrspace(1)* undef
47 declare i32 @llvm.amdgcn.workitem.id.x() #0
48 declare i1 @llvm.amdgcn.is.private(i8* nocapture) #0
50 attributes #0 = { nounwind readnone speculatable }