1 ; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s
2 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s
3 ; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s
5 ; ALL-LABEL: {{^}}test:
6 ; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
7 ; HSA: kernarg_segment_byte_size = 8
8 ; HSA: kernarg_segment_alignment = 4
10 ; CO-V2: s_load_dword s{{[0-9]+}}, s[4:5], 0xa
12 ; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0xa
13 define amdgpu_kernel void @test(i32 addrspace(1)* %out) #1 {
14 %kernarg.segment.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
15 %header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
16 %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
17 %value = load i32, i32 addrspace(4)* %gep
18 store i32 %value, i32 addrspace(1)* %out
22 ; ALL-LABEL: {{^}}test_implicit:
23 ; HSA: kernarg_segment_byte_size = 8
24 ; OS-MESA3D: kernarg_segment_byte_size = 24
25 ; CO-V2: kernarg_segment_alignment = 4
27 ; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15
28 ; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0x15
29 define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 {
30 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
31 %header.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
32 %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
33 %value = load i32, i32 addrspace(4)* %gep
34 store i32 %value, i32 addrspace(1)* %out
38 ; ALL-LABEL: {{^}}test_implicit_alignment:
39 ; HSA: kernarg_segment_byte_size = 12
40 ; OS-MESA3D: kernarg_segment_byte_size = 28
41 ; CO-V2: kernarg_segment_alignment = 4
44 ; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
45 ; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
46 ; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
47 ; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
48 ; MESA: buffer_store_dword [[V_VAL]]
49 ; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
50 define amdgpu_kernel void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #1 {
51 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
52 %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
53 %val = load i32, i32 addrspace(4)* %arg.ptr
54 store i32 %val, i32 addrspace(1)* %out
58 ; ALL-LABEL: {{^}}opencl_test_implicit_alignment
59 ; HSA: kernarg_segment_byte_size = 64
60 ; OS-MESA3D: kernarg_segment_byte_size = 28
61 ; CO-V2: kernarg_segment_alignment = 4
64 ; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
65 ; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
66 ; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
67 ; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
68 ; MESA: buffer_store_dword [[V_VAL]]
69 ; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
70 define amdgpu_kernel void @opencl_test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #2 {
71 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
72 %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
73 %val = load i32, i32 addrspace(4)* %arg.ptr
74 store i32 %val, i32 addrspace(1)* %out
78 ; ALL-LABEL: {{^}}test_no_kernargs:
79 ; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
80 ; HSA: kernarg_segment_byte_size = 0
81 ; OS-MESA3D: kernarg_segment_byte_size = 16
82 ; CO-V2: kernarg_segment_alignment = 4
84 ; HSA: s_load_dword s{{[0-9]+}}, s[4:5]
85 define amdgpu_kernel void @test_no_kernargs() #1 {
86 %kernarg.segment.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
87 %header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
88 %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
89 %value = load i32, i32 addrspace(4)* %gep
90 store volatile i32 %value, i32 addrspace(1)* undef
94 ; GCN-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs:
95 ; HSA: kernarg_segment_byte_size = 48
96 ; OS-MESA3d: kernarg_segment_byte_size = 16
97 ; CO-V2: kernarg_segment_alignment = 4
98 define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs() #2 {
99 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
100 %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
101 %val = load volatile i32, i32 addrspace(4)* %arg.ptr
102 store volatile i32 %val, i32 addrspace(1)* null
106 ; GCN-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs_round_up:
107 ; HSA: kernarg_segment_byte_size = 40
108 ; OS-MESA3D: kernarg_segment_byte_size = 16
109 ; CO-V2: kernarg_segment_alignment = 4
110 define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs_round_up() #3 {
111 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
112 %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
113 %val = load volatile i32, i32 addrspace(4)* %arg.ptr
114 store volatile i32 %val, i32 addrspace(1)* null
118 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
119 declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
121 attributes #0 = { nounwind readnone }
122 attributes #1 = { nounwind }
123 attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="48" }
124 attributes #3 = { nounwind "amdgpu-implicitarg-num-bytes"="38" }