1 ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX906
2 ; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX908
3 ; RUN: llc -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
4 ; RUN: llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
6 declare i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 %clamp)
8 ; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot2_clamp
9 ; GFX906: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
10 ; GFX908: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
11 ; GFX10: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
12 define amdgpu_kernel void @test_llvm_amdgcn_sdot2_clamp(
14 <2 x i16> addrspace(1)* %a,
15 <2 x i16> addrspace(1)* %b,
16 i32 addrspace(1)* %c) {
18 %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
19 %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b
20 %c.val = load i32, i32 addrspace(1)* %c
21 %r.val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 1)
22 store i32 %r.val, i32 addrspace(1)* %r
26 ; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot2_no_clamp
27 ; GFX906: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
28 ; GFX908: v_dot2c_i32_i16_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
29 ; GFX10: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
30 define amdgpu_kernel void @test_llvm_amdgcn_sdot2_no_clamp(
32 <2 x i16> addrspace(1)* %a,
33 <2 x i16> addrspace(1)* %b,
34 i32 addrspace(1)* %c) {
36 %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
37 %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b
38 %c.val = load i32, i32 addrspace(1)* %c
39 %r.val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 0)
40 store i32 %r.val, i32 addrspace(1)* %r