1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
4 ;CHECK-LABEL: {{^}}buffer_load:
5 ;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
6 ;CHECK: buffer_load_dwordx4 v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
7 ;CHECK: buffer_load_dwordx4 v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
11 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
12 %data_glc = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
13 %data_slc = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2)
14 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
15 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
16 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
17 ret {<4 x float>, <4 x float>, <4 x float>} %r2
20 ;CHECK-LABEL: {{^}}buffer_load_immoffs:
21 ;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:40
23 define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {
25 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 40, i32 0, i32 0)
29 ;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
30 ;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1ffc
31 ;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], [[OFFSET]] idxen offset:4
33 define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {
35 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 4, i32 8188, i32 0)
39 ;CHECK-LABEL: {{^}}buffer_load_idx:
40 ;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen
42 define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) {
44 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0)
48 ;CHECK-LABEL: {{^}}buffer_load_ofs:
49 ;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
51 define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {
53 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i32 0, i32 0)
57 ;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
58 ;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
60 define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {
63 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i32 0, i32 0)
67 ;CHECK-LABEL: {{^}}buffer_load_both:
68 ;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
70 define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) {
72 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 %2, i32 0, i32 0)
76 ;CHECK-LABEL: {{^}}buffer_load_both_reversed:
77 ;CHECK: v_mov_b32_e32 v2, v0
78 ;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen
80 define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) {
82 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %2, i32 %1, i32 0, i32 0)
86 ;CHECK-LABEL: {{^}}buffer_load_x1:
87 ;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen
89 define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
91 %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
95 ;CHECK-LABEL: {{^}}buffer_load_x2:
96 ;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen
98 define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
100 %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
101 ret <2 x float> %data
104 ;CHECK-LABEL: {{^}}buffer_load_negative_offset:
105 ;CHECK: v_add_{{[iu]}}32_e32 {{v[0-9]+}}, vcc, -16, v0
106 ;CHECK: buffer_load_dwordx4 v[0:3], {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen
107 define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) {
109 %ofs.1 = add i32 %ofs, -16
110 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs.1, i32 0, i32 0)
111 ret <4 x float> %data
114 ; SI won't merge ds memory operations, because of the signed offset bug, so
115 ; we only have check lines for VI.
116 ; CHECK-LABEL: buffer_load_mmo:
117 ; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
118 ; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4
119 define amdgpu_ps float @buffer_load_mmo(<4 x i32> inreg %rsrc, float addrspace(3)* %lds) {
121 store float 0.0, float addrspace(3)* %lds
122 %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
123 %tmp2 = getelementptr float, float addrspace(3)* %lds, i32 4
124 store float 0.0, float addrspace(3)* %tmp2
128 ;CHECK-LABEL: {{^}}buffer_load_int:
129 ;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
130 ;CHECK: buffer_load_dwordx2 v[4:5], {{v[0-9]+}}, s[0:3], 0 idxen glc
131 ;CHECK: buffer_load_dword v6, {{v[0-9]+}}, s[0:3], 0 idxen slc
133 define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) {
135 %data = call <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
136 %data_glc = call <2 x i32> @llvm.amdgcn.struct.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
137 %data_slc = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2)
138 %fdata = bitcast <4 x i32> %data to <4 x float>
139 %fdata_glc = bitcast <2 x i32> %data_glc to <2 x float>
140 %fdata_slc = bitcast i32 %data_slc to float
141 %r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0
142 %r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1
143 %r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2
144 ret {<4 x float>, <2 x float>, float} %r2
147 ;CHECK-LABEL: {{^}}struct_buffer_load_ubyte:
149 ;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
150 ;CHECK: s_waitcnt vmcnt(0)
151 ;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
152 ;CHECK-NEXT: ; return to shader part epilog
153 define amdgpu_ps float @struct_buffer_load_ubyte(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
155 %tmp = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
156 %tmp2 = zext i8 %tmp to i32
157 %val = uitofp i32 %tmp2 to float
161 ;CHECK-LABEL: {{^}}struct_buffer_load_ushort:
163 ;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
164 ;CHECK-NEXT: s_waitcnt vmcnt(0)
165 ;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
166 ;CHECK-NEXT: ; return to shader part epilog
167 define amdgpu_ps float @struct_buffer_load_ushort(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
169 %tmp = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
170 %tmp2 = zext i16 %tmp to i32
171 %val = uitofp i32 %tmp2 to float
175 ;CHECK-LABEL: {{^}}struct_buffer_load_sbyte:
177 ;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
178 ;CHECK-NEXT: s_waitcnt vmcnt(0)
179 ;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
180 ;CHECK-NEXT: ; return to shader part epilog
181 define amdgpu_ps float @struct_buffer_load_sbyte(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
183 %tmp = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
184 %tmp2 = sext i8 %tmp to i32
185 %val = sitofp i32 %tmp2 to float
189 ;CHECK-LABEL: {{^}}struct_buffer_load_sshort:
191 ;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
192 ;CHECK-NEXT: s_waitcnt vmcnt(0)
193 ;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
194 ;CHECK-NEXT: ; return to shader part epilog
195 define amdgpu_ps float @struct_buffer_load_sshort(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
197 %tmp = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
198 %tmp2 = sext i16 %tmp to i32
199 %val = sitofp i32 %tmp2 to float
203 ;CHECK-LABEL: {{^}}struct_buffer_load_f16:
205 ;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
206 ;CHECK: s_waitcnt vmcnt(0)
207 ;CHECK: ds_write_b16 v0, [[VAL]]
208 define amdgpu_ps void @struct_buffer_load_f16(<4 x i32> inreg %rsrc, half addrspace(3)* %ptr, i32 %idx) {
210 %val = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
211 store half %val, half addrspace(3)* %ptr
215 ;CHECK-LABEL: {{^}}struct_buffer_load_v2f16:
217 ;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
218 ;CHECK: s_waitcnt vmcnt(0)
219 ;CHECK: ds_write_b32 v0, [[VAL]]
220 define amdgpu_ps void @struct_buffer_load_v2f16(<4 x i32> inreg %rsrc, <2 x half> addrspace(3)* %ptr, i32 %idx) {
222 %val = call <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
223 store <2 x half> %val, <2 x half> addrspace(3)* %ptr
227 ;CHECK-LABEL: {{^}}struct_buffer_load_v4f16:
229 ;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], v1, s[0:3], 0 idxen
230 ;CHECK: s_waitcnt vmcnt(0)
231 ;CHECK: ds_write_b64 v0, [[VAL]]
232 define amdgpu_ps void @struct_buffer_load_v4f16(<4 x i32> inreg %rsrc, <4 x half> addrspace(3)* %ptr, i32 %idx) {
234 %val = call <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
235 store <4 x half> %val, <4 x half> addrspace(3)* %ptr
239 ;CHECK-LABEL: {{^}}struct_buffer_load_i16:
241 ;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
242 ;CHECK: s_waitcnt vmcnt(0)
243 ;CHECK: ds_write_b16 v0, [[VAL]]
244 define amdgpu_ps void @struct_buffer_load_i16(<4 x i32> inreg %rsrc, i16 addrspace(3)* %ptr, i32 %idx) {
246 %val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
247 store i16 %val, i16 addrspace(3)* %ptr
251 ;CHECK-LABEL: {{^}}struct_buffer_load_v2i16:
253 ;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
254 ;CHECK: s_waitcnt vmcnt(0)
255 ;CHECK: ds_write_b32 v0, [[VAL]]
256 define amdgpu_ps void @struct_buffer_load_v2i16(<4 x i32> inreg %rsrc, <2 x i16> addrspace(3)* %ptr, i32 %idx) {
258 %val = call <2 x i16> @llvm.amdgcn.struct.buffer.load.v2i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
259 store <2 x i16> %val, <2 x i16> addrspace(3)* %ptr
263 ;CHECK-LABEL: {{^}}struct_buffer_load_v4i16:
265 ;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], v1, s[0:3], 0 idxen
266 ;CHECK: s_waitcnt vmcnt(0)
267 ;CHECK: ds_write_b64 v0, [[VAL]]
268 define amdgpu_ps void @struct_buffer_load_v4i16(<4 x i32> inreg %rsrc, <4 x i16> addrspace(3)* %ptr, i32 %idx) {
270 %val = call <4 x i16> @llvm.amdgcn.struct.buffer.load.v4i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
271 store <4 x i16> %val, <4 x i16> addrspace(3)* %ptr
275 declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32) #0
276 declare <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32>, i32, i32, i32, i32) #0
277 declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #0
278 declare i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32>, i32, i32, i32, i32) #0
279 declare <2 x i32> @llvm.amdgcn.struct.buffer.load.v2i32(<4 x i32>, i32, i32, i32, i32) #0
280 declare <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32>, i32, i32, i32, i32) #0
281 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
282 declare i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32>, i32, i32, i32, i32) #0
284 declare half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32>, i32, i32, i32, i32) #0
285 declare <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32>, i32, i32, i32, i32) #0
286 declare <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32>, i32, i32, i32, i32) #0
288 declare i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32>, i32, i32, i32, i32) #0
289 declare <2 x i16> @llvm.amdgcn.struct.buffer.load.v2i16(<4 x i32>, i32, i32, i32, i32) #0
290 declare <4 x i16> @llvm.amdgcn.struct.buffer.load.v4i16(<4 x i32>, i32, i32, i32, i32) #0
292 attributes #0 = { nounwind readonly }