1 ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX906
2 ; RUN: llc -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
3 ; RUN: llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
5 declare i32 @llvm.amdgcn.udot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 %clamp)
7 ; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_clamp
8 ; GFX906: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
9 ; GFX10: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
10 define amdgpu_kernel void @test_llvm_amdgcn_udot2_clamp(
12 <2 x i16> addrspace(1)* %a,
13 <2 x i16> addrspace(1)* %b,
14 i32 addrspace(1)* %c) {
16 %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
17 %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b
18 %c.val = load i32, i32 addrspace(1)* %c
19 %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 1)
20 store i32 %r.val, i32 addrspace(1)* %r
24 ; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_no_clamp
25 ; GFX906: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
26 ; GFX10: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
27 define amdgpu_kernel void @test_llvm_amdgcn_udot2_no_clamp(
29 <2 x i16> addrspace(1)* %a,
30 <2 x i16> addrspace(1)* %b,
31 i32 addrspace(1)* %c) {
33 %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
34 %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b
35 %c.val = load i32, i32 addrspace(1)* %c
36 %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 0)
37 store i32 %r.val, i32 addrspace(1)* %r