| blob | 15f9657da272b443ec7bcdcb8b512cdab065007c |
1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=FUNC %s
2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=VIGFX9 -check-prefix=FUNC %s
3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=VIGFX9 -check-prefix=FUNC %s
5 declare half @llvm.log10.f16(half %a)
6 declare <2 x half> @llvm.log10.v2f16(<2 x half> %a)
8 ; GCN-LABEL: {{^}}log10_f16
9 ; SI: buffer_load_ushort v[[A_F16_0:[0-9]+]]
10 ; VI: flat_load_ushort v[[A_F16_0:[0-9]+]]
11 ; GFX9: global_load_ushort v[[A_F16_0:[0-9]+]]
12 ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
13 ; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
14 ; SI: v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x3e9a209a, v[[R_F32_0]]
15 ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_1]]
16 ; VIGFX9: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
17 ; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x34d1, v[[R_F16_0]]
18 ; SI: buffer_store_short v[[R_F16_0]], v{{\[[0-9]+:[0-9]+\]}}
19 ; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
20 ; GFX9: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
21 define void @log10_f16(
22 half addrspace(1)* %r,
23 half addrspace(1)* %a) {
24 entry:
25 %a.val = load half, half addrspace(1)* %a
26 %r.val = call half @llvm.log10.f16(half %a.val)
27 store half %r.val, half addrspace(1)* %r
28 ret void
29 }
31 ; GCN-LABEL: {{^}}log10_v2f16
32 ; SI: buffer_load_dword v[[A_F16_0:[0-9]+]]
33 ; VI: flat_load_dword v[[A_F16_0:[0-9]+]]
34 ; GFX9: global_load_dword v[[A_F16_0:[0-9]+]]
35 ; SI: s_mov_b32 [[A_F32_2:s[0-9]+]], 0x3e9a209a
36 ; VIGFX9: s_movk_i32 [[A_F32_2:s[0-9]+]], 0x34d1
37 ; VI: v_mov_b32_e32 [[A_F32_2_V:v[0-9]+]], [[A_F32_2]]
38 ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
39 ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_1]]
40 ; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
41 ; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
42 ; SI: v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
43 ; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], [[A_F32_2]], v[[R_F32_0]]
44 ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]]
45 ; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], [[A_F32_2]], v[[R_F32_1]]
46 ; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]]
47 ; GFX9: v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]]
48 ; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
49 ; VI: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
50 ; VI: v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], [[A_F32_2_V]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
51 ; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], [[A_F32_2]], v[[R_F16_2]]
52 ; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], [[A_F32_2]], v[[R_F16_0]]
53 ; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
54 ; SI-NOT: v_and_b32_e32
55 ; SI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
56 ; VI-NOT: v_and_b32_e32
57 ; VI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_0]], v[[R_F16_2]]
58 ; GFX9: v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]]
59 ; GFX9: v_lshl_or_b32 v[[R_F32_5:[0-9]+]], v[[R_F32_2]], 16, v[[R_F32_4]]
60 ; SI: buffer_store_dword v[[R_F32_5]]
61 ; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
62 ; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
63 define void @log10_v2f16(
64 <2 x half> addrspace(1)* %r,
65 <2 x half> addrspace(1)* %a) {
66 entry:
67 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
68 %r.val = call <2 x half> @llvm.log10.v2f16(<2 x half> %a.val)
69 store <2 x half> %r.val, <2 x half> addrspace(1)* %r
70 ret void
71 }