1 ; RUN: llc -march=r600 -mcpu=redwood -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck %s
3 ; CFG flattening should use parallel-and mode to generate branch conditions and
4 ; then merge if-regions with the same bodies.
10 ; FIXME: For some reason having the allocas here allowed the flatten cfg pass
11 ; to do its transformation, however now that we are using local memory for
12 ; allocas, the transformation isn't happening.
14 define amdgpu_kernel void @_Z9chk1D_512v() #0 {
16 %a0 = alloca i32, align 4, addrspace(5)
17 %b0 = alloca i32, align 4, addrspace(5)
18 %c0 = alloca i32, align 4, addrspace(5)
19 %d0 = alloca i32, align 4, addrspace(5)
20 %a1 = alloca i32, align 4, addrspace(5)
21 %b1 = alloca i32, align 4, addrspace(5)
22 %c1 = alloca i32, align 4, addrspace(5)
23 %d1 = alloca i32, align 4, addrspace(5)
24 %data = alloca i32, align 4, addrspace(5)
25 %0 = load i32, i32 addrspace(5)* %a0, align 4
26 %1 = load i32, i32 addrspace(5)* %b0, align 4
27 %cmp = icmp ne i32 %0, %1
28 br i1 %cmp, label %land.lhs.true, label %if.end
30 land.lhs.true: ; preds = %entry
31 %2 = load i32, i32 addrspace(5)* %c0, align 4
32 %3 = load i32, i32 addrspace(5)* %d0, align 4
33 %cmp1 = icmp ne i32 %2, %3
34 br i1 %cmp1, label %if.then, label %if.end
36 if.then: ; preds = %land.lhs.true
37 store i32 1, i32 addrspace(5)* %data, align 4
40 if.end: ; preds = %if.then, %land.lhs.true, %entry
41 %4 = load i32, i32 addrspace(5)* %a1, align 4
42 %5 = load i32, i32 addrspace(5)* %b1, align 4
43 %cmp2 = icmp ne i32 %4, %5
44 br i1 %cmp2, label %land.lhs.true3, label %if.end6
46 land.lhs.true3: ; preds = %if.end
47 %6 = load i32, i32 addrspace(5)* %c1, align 4
48 %7 = load i32, i32 addrspace(5)* %d1, align 4
49 %cmp4 = icmp ne i32 %6, %7
50 br i1 %cmp4, label %if.then5, label %if.end6
52 if.then5: ; preds = %land.lhs.true3
53 store i32 1, i32 addrspace(5)* %data, align 4
56 if.end6: ; preds = %if.then5, %land.lhs.true3, %if.end