1 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
3 ; RUN: opt -S -mtriple=amdgcn-- -data-layout=A5 -mcpu=fiji -amdgpu-promote-alloca < %s | FileCheck -check-prefix=OPT %s
5 ; GCN-LABEL: {{^}}float4_alloca_store4:
6 ; OPT-LABEL: define amdgpu_kernel void @float4_alloca_store4
11 ; GCN: v_cndmask_b32_e32 [[RES:v[0-9]+]], 4.0,
12 ; GCN: store_dword v[{{[0-9:]+}}], [[RES]]
14 ; OPT: %gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(5)* %alloca, i32 0, i32 %sel2
15 ; OPT: store <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>, <4 x float> addrspace(5)* %alloca, align 4
16 ; OPT: %0 = load <4 x float>, <4 x float> addrspace(5)* %alloca
17 ; OPT: %1 = extractelement <4 x float> %0, i32 %sel2
18 ; OPT: store float %1, float addrspace(1)* %out, align 4
20 define amdgpu_kernel void @float4_alloca_store4(float addrspace(1)* %out, float addrspace(3)* %dummy_lds) {
22 %alloca = alloca <4 x float>, align 16, addrspace(5)
23 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
24 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
25 %c1 = icmp uge i32 %x, 3
26 %c2 = icmp uge i32 %y, 3
27 %sel1 = select i1 %c1, i32 1, i32 2
28 %sel2 = select i1 %c2, i32 0, i32 %sel1
29 %gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(5)* %alloca, i32 0, i32 %sel2
30 store <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, <4 x float> addrspace(5)* %alloca, align 4
31 %load = load float, float addrspace(5)* %gep, align 4
32 store float %load, float addrspace(1)* %out, align 4
36 ; GCN-LABEL: {{^}}float4_alloca_load4:
37 ; OPT-LABEL: define amdgpu_kernel void @float4_alloca_load4
43 ; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
44 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, [[ONE]]
45 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, [[ONE]]
46 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, [[ONE]]
47 ; GCN: store_dwordx4 v[{{[0-9:]+}}],
49 ; OPT: %gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(5)* %alloca, i32 0, i32 %sel2
50 ; OPT: %0 = load <4 x float>, <4 x float> addrspace(5)* %alloca
51 ; OPT: %1 = insertelement <4 x float> %0, float 1.000000e+00, i32 %sel2
52 ; OPT: store <4 x float> %1, <4 x float> addrspace(5)* %alloca
53 ; OPT: %load = load <4 x float>, <4 x float> addrspace(5)* %alloca, align 4
54 ; OPT: store <4 x float> %load, <4 x float> addrspace(1)* %out, align 4
56 define amdgpu_kernel void @float4_alloca_load4(<4 x float> addrspace(1)* %out, float addrspace(3)* %dummy_lds) {
58 %alloca = alloca <4 x float>, align 16, addrspace(5)
59 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
60 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
61 %c1 = icmp uge i32 %x, 3
62 %c2 = icmp uge i32 %y, 3
63 %sel1 = select i1 %c1, i32 1, i32 2
64 %sel2 = select i1 %c2, i32 0, i32 %sel1
65 %gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(5)* %alloca, i32 0, i32 %sel2
66 store float 1.0, float addrspace(5)* %gep, align 4
67 %load = load <4 x float>, <4 x float> addrspace(5)* %alloca, align 4
68 store <4 x float> %load, <4 x float> addrspace(1)* %out, align 4
72 ; GCN-LABEL: {{^}}half4_alloca_store4:
73 ; OPT-LABEL: define amdgpu_kernel void @half4_alloca_store4
76 ; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x44004200
77 ; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x40003c00
78 ; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s{{\[}}[[SL]]:[[SH]]]
80 ; OPT: %gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(5)* %alloca, i32 0, i32 %sel2
81 ; OPT: store <4 x half> <half 0xH3C00, half 0xH4000, half 0xH4200, half 0xH4400>, <4 x half> addrspace(5)* %alloca, align 2
82 ; OPT: %0 = load <4 x half>, <4 x half> addrspace(5)* %alloca
83 ; OPT: %1 = extractelement <4 x half> %0, i32 %sel2
84 ; OPT: store half %1, half addrspace(1)* %out, align 2
86 define amdgpu_kernel void @half4_alloca_store4(half addrspace(1)* %out, half addrspace(3)* %dummy_lds) {
88 %alloca = alloca <4 x half>, align 16, addrspace(5)
89 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
90 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
91 %c1 = icmp uge i32 %x, 3
92 %c2 = icmp uge i32 %y, 3
93 %sel1 = select i1 %c1, i32 1, i32 2
94 %sel2 = select i1 %c2, i32 0, i32 %sel1
95 %gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(5)* %alloca, i32 0, i32 %sel2
96 store <4 x half> <half 1.0, half 2.0, half 3.0, half 4.0>, <4 x half> addrspace(5)* %alloca, align 2
97 %load = load half, half addrspace(5)* %gep, align 2
98 store half %load, half addrspace(1)* %out, align 2
102 ; GCN-LABEL: {{^}}half4_alloca_load4:
103 ; OPT-LABEL: define amdgpu_kernel void @half4_alloca_load4
106 ; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0
107 ; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0xffff
109 ; OPT: %gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(5)* %alloca, i32 0, i32 %sel2
110 ; OPT: %0 = load <4 x half>, <4 x half> addrspace(5)* %alloca
111 ; OPT: %1 = insertelement <4 x half> %0, half 0xH3C00, i32 %sel2
112 ; OPT: store <4 x half> %1, <4 x half> addrspace(5)* %alloca
113 ; OPT: %load = load <4 x half>, <4 x half> addrspace(5)* %alloca, align 2
114 ; OPT: store <4 x half> %load, <4 x half> addrspace(1)* %out, align 2
116 define amdgpu_kernel void @half4_alloca_load4(<4 x half> addrspace(1)* %out, half addrspace(3)* %dummy_lds) {
118 %alloca = alloca <4 x half>, align 16, addrspace(5)
119 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
120 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
121 %c1 = icmp uge i32 %x, 3
122 %c2 = icmp uge i32 %y, 3
123 %sel1 = select i1 %c1, i32 1, i32 2
124 %sel2 = select i1 %c2, i32 0, i32 %sel1
125 %gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(5)* %alloca, i32 0, i32 %sel2
126 store half 1.0, half addrspace(5)* %gep, align 4
127 %load = load <4 x half>, <4 x half> addrspace(5)* %alloca, align 2
128 store <4 x half> %load, <4 x half> addrspace(1)* %out, align 2
132 ; GCN-LABEL: {{^}}short4_alloca_store4:
133 ; OPT-LABEL: define amdgpu_kernel void @short4_alloca_store4
136 ; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x40003
137 ; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x20001
138 ; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s{{\[}}[[SL]]:[[SH]]]
140 ; OPT: %gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(5)* %alloca, i32 0, i32 %sel2
141 ; OPT: store <4 x i16> <i16 1, i16 2, i16 3, i16 4>, <4 x i16> addrspace(5)* %alloca, align 2
142 ; OPT: %0 = load <4 x i16>, <4 x i16> addrspace(5)* %alloca
143 ; OPT: %1 = extractelement <4 x i16> %0, i32 %sel2
144 ; OPT: store i16 %1, i16 addrspace(1)* %out, align 2
146 define amdgpu_kernel void @short4_alloca_store4(i16 addrspace(1)* %out, i16 addrspace(3)* %dummy_lds) {
148 %alloca = alloca <4 x i16>, align 16, addrspace(5)
149 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
150 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
151 %c1 = icmp uge i32 %x, 3
152 %c2 = icmp uge i32 %y, 3
153 %sel1 = select i1 %c1, i32 1, i32 2
154 %sel2 = select i1 %c2, i32 0, i32 %sel1
155 %gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(5)* %alloca, i32 0, i32 %sel2
156 store <4 x i16> <i16 1, i16 2, i16 3, i16 4>, <4 x i16> addrspace(5)* %alloca, align 2
157 %load = load i16, i16 addrspace(5)* %gep, align 2
158 store i16 %load, i16 addrspace(1)* %out, align 2
162 ; GCN-LABEL: {{^}}short4_alloca_load4:
163 ; OPT-LABEL: define amdgpu_kernel void @short4_alloca_load4
166 ; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0
167 ; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0xffff
169 ; OPT: %gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(5)* %alloca, i32 0, i32 %sel2
170 ; OPT: %0 = load <4 x i16>, <4 x i16> addrspace(5)* %alloca
171 ; OPT: %1 = insertelement <4 x i16> %0, i16 1, i32 %sel2
172 ; OPT: store <4 x i16> %1, <4 x i16> addrspace(5)* %alloca
173 ; OPT: %load = load <4 x i16>, <4 x i16> addrspace(5)* %alloca, align 2
174 ; OPT: store <4 x i16> %load, <4 x i16> addrspace(1)* %out, align 2
176 define amdgpu_kernel void @short4_alloca_load4(<4 x i16> addrspace(1)* %out, i16 addrspace(3)* %dummy_lds) {
178 %alloca = alloca <4 x i16>, align 16, addrspace(5)
179 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
180 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
181 %c1 = icmp uge i32 %x, 3
182 %c2 = icmp uge i32 %y, 3
183 %sel1 = select i1 %c1, i32 1, i32 2
184 %sel2 = select i1 %c2, i32 0, i32 %sel1
185 %gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(5)* %alloca, i32 0, i32 %sel2
186 store i16 1, i16 addrspace(5)* %gep, align 4
187 %load = load <4 x i16>, <4 x i16> addrspace(5)* %alloca, align 2
188 store <4 x i16> %load, <4 x i16> addrspace(1)* %out, align 2
192 declare i32 @llvm.amdgcn.workitem.id.x()
193 declare i32 @llvm.amdgcn.workitem.id.y()