1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s
3 ; FUNC-LABEL: {{^}}s_add_i32:
4 ; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 define amdgpu_kernel void @s_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
6 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
7 %a = load i32, i32 addrspace(1)* %in
8 %b = load i32, i32 addrspace(1)* %b_ptr
9 %result = add i32 %a, %b
10 store i32 %result, i32 addrspace(1)* %out
14 ; FUNC-LABEL: {{^}}s_add_v2i32:
15 ; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
16 ; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
17 define amdgpu_kernel void @s_add_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
18 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
19 %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
20 %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
21 %result = add <2 x i32> %a, %b
22 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
26 ; FUNC-LABEL: {{^}}s_add_v4i32:
27 ; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
30 ; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
31 define amdgpu_kernel void @s_add_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
32 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
33 %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
34 %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
35 %result = add <4 x i32> %a, %b
36 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
40 ; FUNC-LABEL: {{^}}s_add_v8i32:
49 define amdgpu_kernel void @s_add_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) {
51 %0 = add <8 x i32> %a, %b
52 store <8 x i32> %0, <8 x i32> addrspace(1)* %out
56 ; FUNC-LABEL: {{^}}s_add_v16i32:
73 define amdgpu_kernel void @s_add_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) {
75 %0 = add <16 x i32> %a, %b
76 store <16 x i32> %0, <16 x i32> addrspace(1)* %out
80 ; FUNC-LABEL: {{^}}v_add_i32:
81 define amdgpu_kernel void @v_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
82 %tid = call i32 @llvm.r600.read.tidig.x()
83 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
84 %b_ptr = getelementptr i32, i32 addrspace(1)* %gep, i32 1
85 %a = load volatile i32, i32 addrspace(1)* %gep
86 %b = load volatile i32, i32 addrspace(1)* %b_ptr
87 %result = add i32 %a, %b
88 store i32 %result, i32 addrspace(1)* %out
92 ; FUNC-LABEL: {{^}}v_add_imm_i32:
93 define amdgpu_kernel void @v_add_imm_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
94 %tid = call i32 @llvm.r600.read.tidig.x()
95 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
96 %b_ptr = getelementptr i32, i32 addrspace(1)* %gep, i32 1
97 %a = load volatile i32, i32 addrspace(1)* %gep
98 %result = add i32 %a, 123
99 store i32 %result, i32 addrspace(1)* %out
103 ; FUNC-LABEL: {{^}}add64:
104 ; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]]
105 ; EG-DAG: ADD_INT {{[* ]*}}
108 ; EG-DAG: ADD_INT {{[* ]*}}
110 define amdgpu_kernel void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
112 %add = add i64 %a, %b
113 store i64 %add, i64 addrspace(1)* %out
117 ; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
118 ; use VCC. The test is designed so that %a will be stored in an SGPR and
119 ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
120 ; to a VGPR before doing the add.
122 ; FUNC-LABEL: {{^}}add64_sgpr_vgpr:
123 ; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]]
124 ; EG-DAG: ADD_INT {{[* ]*}}
127 ; EG-DAG: ADD_INT {{[* ]*}}
129 define amdgpu_kernel void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
131 %0 = load i64, i64 addrspace(1)* %in
133 store i64 %1, i64 addrspace(1)* %out
137 ; Test i64 add inside a branch.
138 ; FUNC-LABEL: {{^}}add64_in_branch:
139 ; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]]
140 ; EG-DAG: ADD_INT {{[* ]*}}
143 ; EG-DAG: ADD_INT {{[* ]*}}
145 define amdgpu_kernel void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
147 %0 = icmp eq i64 %a, 0
148 br i1 %0, label %if, label %else
151 %1 = load i64, i64 addrspace(1)* %in
159 %3 = phi i64 [%1, %if], [%2, %else]
160 store i64 %3, i64 addrspace(1)* %out
164 declare i32 @llvm.r600.read.tidig.x() #1
166 attributes #0 = { nounwind }
167 attributes #1 = { nounwind readnone speculatable }