1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
5 ; FUNC-LABEL: {{^}}rotl_i32:
6 ; R600: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
8 ; R600: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}}
10 ; SI: s_sub_i32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}}
11 ; SI: v_mov_b32_e32 [[VDST:v[0-9]+]], [[SDST]]
12 ; SI: v_alignbit_b32 {{v[0-9]+, [s][0-9]+, s[0-9]+}}, [[VDST]]
13 define amdgpu_kernel void @rotl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) {
19 store i32 %3, i32 addrspace(1)* %in
23 ; FUNC-LABEL: {{^}}rotl_v2i32:
26 ; SI-DAG: v_alignbit_b32
27 ; SI-DAG: v_alignbit_b32
29 define amdgpu_kernel void @rotl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
31 %0 = shl <2 x i32> %x, %y
32 %1 = sub <2 x i32> <i32 32, i32 32>, %y
33 %2 = lshr <2 x i32> %x, %1
34 %3 = or <2 x i32> %0, %2
35 store <2 x i32> %3, <2 x i32> addrspace(1)* %in
39 ; FUNC-LABEL: {{^}}rotl_v4i32:
41 ; SI-DAG: v_alignbit_b32
43 ; SI-DAG: v_alignbit_b32
45 ; SI-DAG: v_alignbit_b32
47 ; SI-DAG: v_alignbit_b32
49 define amdgpu_kernel void @rotl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
51 %0 = shl <4 x i32> %x, %y
52 %1 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
53 %2 = lshr <4 x i32> %x, %1
54 %3 = or <4 x i32> %0, %2
55 store <4 x i32> %3, <4 x i32> addrspace(1)* %in