| blob | dbe03109b819539814a4d4b740e50641eb394776 |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s
4 # The sequence of DBG_VALUEs forms a scheduling region with 0 real
5 # instructions. The RegPressure tracker would end up skipping over any
6 # debug instructions, so it would point to the instruction
7 # before/outside of the region, hitting this assert:
8 # assert((BotRPTracker.getPos() == RegionEnd ||
9 # (RegionEnd->isDebugInstr() &&
10 # BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&
11 # "Can't find the region bottom");
13 ---
14 name: only_dbg_value_sched_region
15 tracksRegLiveness: true
16 machineFunctionInfo:
17 isEntryFunction: true
18 waveLimiter: true
19 body: |
20 ; CHECK-LABEL: name: only_dbg_value_sched_region
21 ; CHECK: bb.0:
22 ; CHECK: successors: %bb.1(0x80000000)
23 ; CHECK: liveins: $vgpr0
24 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
25 ; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
26 ; CHECK: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, 0, 0, implicit $exec
27 ; CHECK: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, 0, 0, implicit $exec
28 ; CHECK: undef %4.sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec
29 ; CHECK: %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
30 ; CHECK: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
31 ; CHECK: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
32 ; CHECK: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
33 ; CHECK: undef %11.sub1:vreg_64 = IMPLICIT_DEF
34 ; CHECK: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
35 ; CHECK: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
36 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
37 ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
38 ; CHECK: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
39 ; CHECK: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
40 ; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]]
41 ; CHECK: undef %6.sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $exec
42 ; CHECK: dead undef %6.sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $exec
43 ; CHECK: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, 0, 0, implicit $exec
44 ; CHECK: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
45 ; CHECK: undef %19.sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $exec
46 ; CHECK: %19.sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $exec
47 ; CHECK: GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, 0, implicit $exec
48 ; CHECK: %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF1]], 0, 0, 0, 0, implicit $exec
49 ; CHECK: [[DEF2]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF3]], 0, 0, 0, 0, implicit $exec
50 ; CHECK: dead %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, 0, implicit $exec
51 ; CHECK: dead %21:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF4]], 0, 0, 0, 0, implicit $exec
52 ; CHECK: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 2, [[DEF2]], implicit $exec
53 ; CHECK: dead %22:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF5]], 0, 0, 0, 0, implicit $exec
54 ; CHECK: S_NOP 0, implicit [[DEF7]], implicit [[V_LSHLREV_B64_]].sub0, implicit [[DEF6]], implicit [[V_MOV_B32_e32_]]
55 ; CHECK: GLOBAL_STORE_DWORD [[DEF5]], [[V_MOV_B32_e32_1]], 0, 0, 0, 0, implicit $exec
56 ; CHECK: bb.1:
57 ; CHECK: successors: %bb.2(0x80000000)
58 ; CHECK: S_SETREG_IMM32_B32 0, 1
59 ; CHECK: DBG_VALUE
60 ; CHECK: DBG_VALUE
61 ; CHECK: DBG_VALUE
62 ; CHECK: S_SETREG_IMM32_B32 0, 1
63 ; CHECK: bb.2:
64 ; CHECK: S_NOP 0, implicit [[COPY]]
65 ; CHECK: S_NOP 0, implicit [[DEF8]]
66 ; CHECK: S_ENDPGM 0
67 bb.0:
68 liveins: $vgpr0
70 %0:vgpr_32 = COPY $vgpr0
71 %1:vreg_64 = IMPLICIT_DEF
72 %2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, 0, 0, implicit $exec
73 %3:vgpr_32 = GLOBAL_LOAD_DWORD %1, 8, 0, 0, 0, implicit $exec
74 undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0, %0, implicit $exec
75 %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
76 %5:vreg_64 = COPY %2
77 undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0, %5.sub0, implicit $exec
78 %6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1, %5.sub0, implicit $exec
79 %7:vgpr_32 = GLOBAL_LOAD_DWORD %5, 0, 0, 0, 0, implicit $exec
80 %8:vreg_64 = IMPLICIT_DEF
81 %9:vreg_64 = IMPLICIT_DEF
82 %10:vreg_64 = IMPLICIT_DEF
83 undef %11.sub1:vreg_64 = IMPLICIT_DEF
84 %12:vgpr_32 = IMPLICIT_DEF
85 %13:vgpr_32 = IMPLICIT_DEF
86 %14:vreg_64 = IMPLICIT_DEF
87 %15:vreg_64 = IMPLICIT_DEF
88 %16:vgpr_32 = IMPLICIT_DEF
89 %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
90 %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
91 undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7, %2.sub0, implicit $exec
92 %19.sub1:vreg_64 = V_ADD_F32_e32 %3, %3, implicit $exec
93 GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, 0, implicit $exec
94 %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9, 0, 0, 0, 0, implicit $exec
95 %8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10, 0, 0, 0, 0, implicit $exec
96 %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, 0, implicit $exec
97 %21:vgpr_32 = GLOBAL_LOAD_DWORD %14, 0, 0, 0, 0, implicit $exec
98 %22:vgpr_32 = GLOBAL_LOAD_DWORD %15, 0, 0, 0, 0, implicit $exec
99 %23:vreg_64 = V_LSHLREV_B64 2, %8, implicit $exec
100 S_NOP 0, implicit %13, implicit %23.sub0, implicit %12, implicit %17
101 GLOBAL_STORE_DWORD %15, %18, 0, 0, 0, 0, implicit $exec
103 bb.1:
104 S_SETREG_IMM32_B32 0, 1
105 DBG_VALUE
106 DBG_VALUE
107 DBG_VALUE
108 S_SETREG_IMM32_B32 0, 1
110 bb.2:
111 S_NOP 0, implicit %0
112 S_NOP 0, implicit %16
113 S_ENDPGM 0
115 ...