| blob | b954b778dc6531034039054c49fc3d1ebd7e6b82 |
1 # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s
3 --- |
4 %struct.widget.0 = type { float, i32, i32 }
5 %struct.baz = type { <4 x float>, <4 x float>, <2 x float>, i32, i32 }
6 %struct.snork = type { float, float, float, i32, float, float, float, float, %struct.spam }
7 %struct.spam = type { %struct.zot, [16 x i8] }
8 %struct.zot = type { float, float, float, float, <4 x float> }
9 %struct.wombat = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, [2 x i16], [2 x i16] }
10 %struct.wombat.1 = type { [4 x i32], [4 x i32], [4 x i32], [4 x i32], i32, i32, i32, i32 }
12 @sched_dbg_value_crash.tmp6 = internal unnamed_addr addrspace(3) global [256 x [16 x i8]] undef, align 16
14 define amdgpu_kernel void @sched_dbg_value_crash(i8 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture readonly %arg1, %struct.widget.0 addrspace(1)* nocapture readonly %arg2, %struct.baz addrspace(1)* nocapture readonly %arg3, %struct.snork addrspace(1)* nocapture %arg4) local_unnamed_addr #2 {
15 bb:
16 %0 = getelementptr i32, i32 addrspace(1)* %arg1, i64 0, !amdgpu.uniform !3, !amdgpu.noclobber !3
17 %tmp5 = alloca %struct.wombat, align 16, addrspace(5)
18 %1 = call noalias nonnull dereferenceable(64) i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
19 %2 = bitcast i8 addrspace(4)* %1 to i32 addrspace(4)*
20 %3 = getelementptr inbounds i32, i32 addrspace(4)* %2, i64 1
21 %4 = bitcast i32 addrspace(4)* %3 to <2 x i32> addrspace(4)*, !amdgpu.uniform !3, !amdgpu.noclobber !3
22 %5 = load <2 x i32>, <2 x i32> addrspace(4)* %4, align 4, !invariant.load !3
23 %6 = extractelement <2 x i32> %5, i32 0
24 %7 = extractelement <2 x i32> %5, i32 1
25 %8 = lshr i32 %6, 16
26 %9 = call i32 @llvm.amdgcn.workitem.id.x(), !range !4
27 %10 = call i32 @llvm.amdgcn.workitem.id.y(), !range !4
28 %11 = call i32 @llvm.amdgcn.workitem.id.z(), !range !4
29 %12 = mul nuw nsw i32 %8, %7
30 %13 = mul i32 %12, %9
31 %14 = mul nuw nsw i32 %10, %7
32 %15 = add i32 %13, %14
33 %16 = add i32 %15, %11
34 %17 = getelementptr inbounds [256 x [16 x i8]], [256 x [16 x i8]] addrspace(3)* @sched_dbg_value_crash.tmp6, i32 0, i32 %16
35 %tmp7 = load i64, i64 addrspace(4)* null, align 536870912
36 %tmp8 = tail call i32 @llvm.amdgcn.workitem.id.x() #3, !range !4
37 %tmp9 = zext i32 %tmp8 to i64
38 %tmp10 = add i64 %tmp7, %tmp9
39 %tmp11 = shl i64 %tmp10, 32
40 %tmp12 = ashr exact i64 %tmp11, 32
41 %tmp13 = getelementptr inbounds %struct.widget.0, %struct.widget.0 addrspace(1)* %arg2, i64 %tmp12, i32 1
42 %tmp14 = load i32, i32 addrspace(1)* %tmp13, align 4
43 %tmp15 = getelementptr inbounds %struct.baz, %struct.baz addrspace(1)* %arg3, i64 %tmp12, i32 1
44 %tmp16 = load <4 x float>, <4 x float> addrspace(1)* %tmp15, align 16
45 %tmp17 = sext i32 %tmp14 to i64
46 %tmp18 = load i32, i32 addrspace(1)* %0, align 4
47 %tmp19 = zext i32 %tmp18 to i64
48 %tmp20 = shl nuw nsw i64 %tmp19, 2
49 %tmp21 = getelementptr inbounds i8, i8 addrspace(1)* %arg, i64 %tmp20
50 %tmp22 = bitcast i8 addrspace(1)* %tmp21 to %struct.wombat.1 addrspace(1)*
51 %tmp23 = bitcast %struct.wombat addrspace(5)* %tmp5 to i8 addrspace(5)*
52 call void @llvm.lifetime.start.p5i8(i64 144, i8 addrspace(5)* nonnull %tmp23) #3
53 %tmp24 = getelementptr inbounds %struct.wombat, %struct.wombat addrspace(5)* %tmp5, i32 0, i32 6
54 %tmp25 = getelementptr i32, i32 addrspace(1)* %arg1, i64 3, !amdgpu.uniform !3, !amdgpu.noclobber !3
55 %tmp26 = load i32, i32 addrspace(1)* %tmp25, align 4
56 %tmp27 = zext i32 %tmp26 to i64
57 %tmp28 = shl nuw nsw i64 %tmp27, 2
58 %tmp29 = getelementptr inbounds i8, i8 addrspace(1)* %arg, i64 %tmp28
59 %tmp30 = bitcast i8 addrspace(1)* %tmp29 to <2 x float> addrspace(1)*
60 %tmp31 = getelementptr inbounds %struct.wombat.1, %struct.wombat.1 addrspace(1)* %tmp22, i64 %tmp17, i32 2, i64 0
61 %18 = bitcast i32 addrspace(1)* %tmp31 to <3 x i32> addrspace(1)*
62 %19 = load <3 x i32>, <3 x i32> addrspace(1)* %18, align 4
63 %tmp325 = extractelement <3 x i32> %19, i32 0
64 %tmp386 = extractelement <3 x i32> %19, i32 1
65 %tmp447 = extractelement <3 x i32> %19, i32 2
66 %tmp33 = sext i32 %tmp325 to i64
67 %tmp34 = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %tmp30, i64 %tmp33
68 %tmp35 = load <2 x float>, <2 x float> addrspace(1)* %tmp34, align 8
69 %tmp36 = extractelement <2 x float> %tmp35, i32 1
70 %tmp39 = sext i32 %tmp386 to i64
71 %tmp40 = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %tmp30, i64 %tmp39
72 %tmp41 = load <2 x float>, <2 x float> addrspace(1)* %tmp40, align 8
73 %tmp42 = extractelement <2 x float> %tmp41, i32 1
74 %tmp45 = sext i32 %tmp447 to i64
75 %tmp46 = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %tmp30, i64 %tmp45
76 %tmp47 = load <2 x float>, <2 x float> addrspace(1)* %tmp46, align 8
77 %tmp48 = extractelement <2 x float> %tmp47, i32 1
78 %tmp49 = getelementptr i32, i32 addrspace(1)* %arg1, i64 1, !amdgpu.uniform !3, !amdgpu.noclobber !3
79 %tmp50 = load i32, i32 addrspace(1)* %tmp49, align 4
80 %tmp51 = zext i32 %tmp50 to i64
81 %tmp52 = shl nuw nsw i64 %tmp51, 2
82 %tmp53 = getelementptr inbounds i8, i8 addrspace(1)* %arg, i64 %tmp52
83 %tmp54 = bitcast i8 addrspace(1)* %tmp53 to <4 x float> addrspace(1)*
84 %tmp55 = getelementptr inbounds %struct.wombat.1, %struct.wombat.1 addrspace(1)* %tmp22, i64 %tmp17, i32 0, i64 0
85 %20 = bitcast i32 addrspace(1)* %tmp55 to <2 x i32> addrspace(1)*
86 %21 = load <2 x i32>, <2 x i32> addrspace(1)* %20, align 4
87 %tmp568 = extractelement <2 x i32> %21, i32 0
88 %tmp639 = extractelement <2 x i32> %21, i32 1
89 %tmp57 = sext i32 %tmp568 to i64
90 %tmp58 = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %tmp54, i64 %tmp57
91 %tmp59 = load <4 x float>, <4 x float> addrspace(1)* %tmp58, align 16
92 %tmp60 = extractelement <4 x float> %tmp59, i32 0
93 %tmp61 = extractelement <4 x float> %tmp59, i32 1
94 %tmp64 = sext i32 %tmp639 to i64
95 %tmp65 = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %tmp54, i64 %tmp64
96 %tmp66 = load <4 x float>, <4 x float> addrspace(1)* %tmp65, align 16
97 %tmp67 = extractelement <4 x float> %tmp16, i64 0
98 %tmp69 = fsub fast float -0.000000e+00, %tmp67
99 %tmp70 = fmul float %tmp67, 0.000000e+00
100 %tmp = fmul fast float %tmp67, undef
101 %tmp71 = fsub fast float %tmp, %tmp70
102 %tmp73 = fadd fast float %tmp, undef
103 %tmp74 = insertelement <4 x float> <float undef, float undef, float undef, float 0.000000e+00>, float %tmp69, i32 0
104 %tmp75 = insertelement <4 x float> %tmp74, float %tmp71, i32 1
105 %tmp76 = insertelement <4 x float> %tmp75, float %tmp73, i32 2
106 store <4 x float> %tmp76, <4 x float> addrspace(5)* %tmp24, align 16
107 %tmp77 = fsub float undef, %tmp60
108 %tmp78 = fsub float undef, %tmp61
109 %tmp79 = extractelement <4 x float> %tmp66, i32 2
110 %tmp80 = extractelement <4 x float> %tmp59, i32 2
111 %tmp81 = fsub float %tmp79, %tmp80
112 %tmp82 = fmul fast float %tmp81, undef
113 %tmp83 = fmul fast float %tmp78, undef
114 %tmp84 = fadd fast float %tmp83, %tmp77
115 %tmp85 = fadd fast float %tmp84, undef
116 %tmp86 = fmul float %tmp82, %tmp82
117 %tmp87 = fdiv float 1.000000e+00, %tmp86
118 tail call void @llvm.dbg.value(metadata float %tmp87, metadata !5, metadata !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)) #3, !dbg !8
119 %tmp88 = fmul float %tmp82, 0.000000e+00
120 %tmp89 = fsub fast float %tmp85, %tmp88
121 %tmp90 = fdiv float %tmp89, %tmp86
122 %tmp91 = fsub float 1.000000e+00, %tmp87
123 %tmp92 = fsub float %tmp91, %tmp90
124 %tmp93 = fmul float %tmp42, %tmp87
125 %tmp94 = call float @llvm.fmuladd.f32(float %tmp92, float %tmp36, float %tmp93)
126 %tmp95 = call float @llvm.fmuladd.f32(float %tmp48, float undef, float %tmp94)
127 %tmp96 = fsub float extractelement (<2 x float> fadd (<2 x float> fmul (<2 x float> undef, <2 x float> undef), <2 x float> undef), i64 1), %tmp95
128 %tmp97 = getelementptr inbounds %struct.wombat, %struct.wombat addrspace(5)* %tmp5, i32 0, i32 8, i32 1
129 call void @func(float %tmp96, i64 0, i16 addrspace(5)* nonnull %tmp97) #3
130 %tmp984 = bitcast [16 x i8] addrspace(3)* %17 to i8 addrspace(3)*
131 %tmp99 = getelementptr inbounds %struct.snork, %struct.snork addrspace(1)* %arg4, i64 %tmp12, i32 8, i32 1, i64 0
132 call void @llvm.memcpy.p1i8.p3i8.i64(i8 addrspace(1)* %tmp99, i8 addrspace(3)* %tmp984, i64 16, i32 16, i1 false)
133 call void @llvm.lifetime.end.p5i8(i64 144, i8 addrspace(5)* nonnull %tmp23) #3
134 ret void
135 }
137 declare void @func(float, i64, i16 addrspace(5)*)
138 declare void @llvm.lifetime.start.p5i8(i64, i8 addrspace(5)* nocapture) #0
139 declare float @llvm.fmuladd.f32(float, float, float) #1
140 declare void @llvm.lifetime.end.p5i8(i64, i8 addrspace(5)* nocapture) #0
141 declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
142 declare i32 @llvm.amdgcn.workitem.id.x() #1
143 declare void @llvm.dbg.value(metadata, metadata, metadata) #1
144 declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #1
145 declare i32 @llvm.amdgcn.workitem.id.y() #1
146 declare i32 @llvm.amdgcn.workitem.id.z() #1
147 declare void @llvm.memcpy.p1i8.p5i8.i64(i8 addrspace(1)* nocapture writeonly, i8 addrspace(5)* nocapture readonly, i64, i32, i1) #0
148 declare void @llvm.memcpy.p1i8.p3i8.i64(i8 addrspace(1)* nocapture writeonly, i8 addrspace(3)* nocapture readonly, i64, i32, i1) #0
150 attributes #0 = { argmemonly nounwind }
151 attributes #1 = { nounwind readnone speculatable }
152 attributes #2 = { convergent nounwind "amdgpu-dispatch-ptr" "amdgpu-flat-scratch" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "target-cpu"="gfx900" "target-features"="+fp32-denormals" }
153 attributes #3 = { nounwind }
155 !llvm.dbg.cu = !{!0}
156 !llvm.module.flags = !{!2}
158 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
159 !1 = !DIFile(filename: "foo.cl", directory: "/dev/null")
160 !2 = !{i32 2, !"Debug Info Version", i32 3}
161 !3 = !{}
162 !4 = !{i32 0, i32 256}
163 !5 = !DILocalVariable(name: "bar", scope: !6, file: !1, line: 102, type: !7)
164 !6 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 81, isLocal: false, isDefinition: true, scopeLine: 86, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
165 !7 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
166 !8 = !DILocation(line: 102, column: 8, scope: !6)
168 ...
169 ---
171 # CHECK: name: sched_dbg_value_crash
172 # CHECK: DBG_VALUE %99, $noreg, !5, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !8
174 name: sched_dbg_value_crash
175 alignment: 1
176 exposesReturnsTwice: false
177 legalized: false
178 regBankSelected: false
179 selected: false
180 tracksRegLiveness: true
181 liveins:
182 - { reg: '$vgpr0', virtual-reg: '%0' }
183 - { reg: '$vgpr1', virtual-reg: '%1' }
184 - { reg: '$vgpr2', virtual-reg: '%2' }
185 - { reg: '$sgpr4_sgpr5', virtual-reg: '%3' }
186 - { reg: '$sgpr6_sgpr7', virtual-reg: '%4' }
187 fixedStack:
188 stack:
189 - { id: 0, name: tmp5, type: default, offset: 0, size: 128, alignment: 16,
190 stack-id: default, callee-saved-register: '', callee-saved-restored: true,
191 local-offset: 0, debug-info-variable: '', debug-info-expression: '',
192 debug-info-location: '' }
193 constants:
194 body: |
195 bb.0.bb:
196 liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr32, $sgpr101
198 %4:sgpr_64 = COPY $sgpr6_sgpr7
199 %3:sgpr_64 = COPY $sgpr4_sgpr5
200 %2:vgpr_32 = COPY $vgpr2
201 %1:vgpr_32 = COPY $vgpr1
202 %0:vgpr_32 = COPY $vgpr0
203 %5:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 0, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
204 %6:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 8, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
205 %7:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 16, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
206 %8:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 24, 0, 0
207 %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 32, 0, 0
208 %10:sreg_64_xexec = S_LOAD_DWORDX2_IMM %3, 4, 0, 0
209 %11:sreg_32_xm0 = S_LSHR_B32 %10.sub0, 16, implicit-def dead $scc
210 %12:sreg_32_xm0 = S_MUL_I32 %11, %10.sub1
211 %13:vgpr_32 = V_MUL_LO_I32 0, %0, implicit $exec
212 %14:vgpr_32 = V_MUL_LO_I32 %1, %10.sub1, implicit $exec
213 %15:vgpr_32 = V_ADD_I32_e32 0, %13, implicit-def dead $vcc, implicit $exec
214 %16:vgpr_32 = V_ADD_I32_e32 0, %15, implicit-def dead $vcc, implicit $exec
215 %17:vgpr_32 = IMPLICIT_DEF
216 %18:sreg_64 = S_MOV_B64 0
217 %19:sreg_32_xm0_xexec = IMPLICIT_DEF
218 %20:vgpr_32 = V_ADD_I32_e32 %19, %0, implicit-def dead $vcc, implicit $exec
219 %21:vreg_64, dead %22:sreg_64 = V_MAD_I64_I32 %20, 12, %7, 0, implicit $exec
220 %23:vgpr_32 = GLOBAL_LOAD_DWORD %21, 4, 0, 0, 0, implicit $exec
221 %24:vreg_64, dead %25:sreg_64 = V_MAD_I64_I32 %20, 48, %8, 0, implicit $exec
222 %26:vreg_128 = IMPLICIT_DEF
223 undef %27.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %6, 0, 0, 0
224 %27.sub1:sreg_64_xexec = S_MOV_B32 0
225 %28:sreg_64 = S_LSHL_B64 %27, 2, implicit-def dead $scc
226 undef %29.sub0:sreg_64 = S_ADD_U32 %5.sub0, %28.sub0, implicit-def $scc
227 %29.sub1:sreg_64 = S_ADDC_U32 %5.sub1, %28.sub1, implicit-def dead $scc, implicit killed $scc
228 undef %30.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %6, 4, 0, 0
229 %27.sub0:sreg_64_xexec = IMPLICIT_DEF
230 %31:sreg_64 = S_LSHL_B64 %27, 2, implicit-def dead $scc
231 %32:sreg_32_xm0 = S_ADD_U32 0, %31.sub0, implicit-def $scc
232 %33:sgpr_32 = S_ADDC_U32 %5.sub1, %31.sub1, implicit-def dead $scc, implicit killed $scc
233 %34:vgpr_32 = IMPLICIT_DEF
234 %35:vreg_64, dead %36:sreg_64 = V_MAD_I64_I32 %23, %34, 0, 0, implicit $exec
235 %37:vreg_64 = GLOBAL_LOAD_DWORDX2 %35, 32, 0, 0, 0, implicit $exec
236 undef %38.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %37.sub0, implicit $exec
237 %38.sub0:vreg_64 = COPY %37.sub0
238 %39:vreg_64 = V_LSHLREV_B64 3, %38, implicit $exec
239 undef %40.sub0:vreg_64, %41:sreg_64_xexec = V_ADD_I32_e64 0, %39.sub0, 0, implicit $exec
240 %42:vgpr_32 = COPY %33
241 %40.sub1:vreg_64, dead %43:sreg_64_xexec = V_ADDC_U32_e64 %42, %39.sub1, %41, 0, implicit $exec
242 %44:vreg_64 = GLOBAL_LOAD_DWORDX2 %40, 0, 0, 0, 0, implicit $exec :: (load 8 from %ir.tmp34)
243 undef %45.sub1:vreg_64 = IMPLICIT_DEF
244 %45.sub0:vreg_64 = COPY %37.sub1
245 %46:vreg_64 = V_LSHLREV_B64 3, %45, implicit $exec
246 undef %47.sub0:vreg_64, %48:sreg_64_xexec = V_ADD_I32_e64 %32, %46.sub0, 0, implicit $exec
247 %49:vgpr_32 = COPY %33
248 %47.sub1:vreg_64, dead %50:sreg_64_xexec = V_ADDC_U32_e64 %49, %46.sub1, %48, 0, implicit $exec
249 %51:vreg_64 = IMPLICIT_DEF
250 undef %52.sub0:vreg_64 = GLOBAL_LOAD_DWORD %35, 40, 0, 0, 0, implicit $exec :: (load 4 from %ir.18 + 8)
251 %52.sub1:vreg_64 = IMPLICIT_DEF
252 %53:vreg_64 = V_LSHLREV_B64 3, %52, implicit $exec
253 undef %54.sub0:vreg_64, %55:sreg_64_xexec = V_ADD_I32_e64 0, %53.sub0, 0, implicit $exec
254 %56:vgpr_32 = COPY %33
255 %54.sub1:vreg_64, dead %57:sreg_64_xexec = V_ADDC_U32_e64 0, %53.sub1, %55, 0, implicit $exec
256 %58:vreg_64 = IMPLICIT_DEF
257 %30.sub1:sreg_64_xexec = IMPLICIT_DEF
258 %59:sreg_64 = IMPLICIT_DEF
259 %60:sreg_32_xm0 = S_ADD_U32 %5.sub0, %59.sub0, implicit-def $scc
260 %61:sgpr_32 = S_ADDC_U32 %5.sub1, %59.sub1, implicit-def dead $scc, implicit killed $scc
261 %62:vreg_64 = GLOBAL_LOAD_DWORDX2 %35, 0, 0, 0, 0, implicit $exec :: (load 8 from %ir.20, align 4)
262 undef %63.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %62.sub0, implicit $exec
263 %63.sub0:vreg_64 = COPY %62.sub0
264 %64:vreg_64 = IMPLICIT_DEF
265 undef %65.sub0:vreg_64, %66:sreg_64_xexec = V_ADD_I32_e64 %60, %64.sub0, 0, implicit $exec
266 %67:vgpr_32 = COPY %61
267 %65.sub1:vreg_64, dead %68:sreg_64_xexec = V_ADDC_U32_e64 %67, %64.sub1, %66, 0, implicit $exec
268 %69:vreg_128 = GLOBAL_LOAD_DWORDX4 %65, 0, 0, 0, 0, implicit $exec :: (load 16 from %ir.tmp58)
269 undef %70.sub1:vreg_64 = IMPLICIT_DEF
270 %70.sub0:vreg_64 = IMPLICIT_DEF
271 %71:vreg_64 = IMPLICIT_DEF
272 undef %72.sub0:vreg_64, %73:sreg_64_xexec = V_ADD_I32_e64 %60, %71.sub0, 0, implicit $exec
273 %74:vgpr_32 = COPY %61
274 %72.sub1:vreg_64, dead %75:sreg_64_xexec = V_ADDC_U32_e64 0, %71.sub1, %73, 0, implicit $exec
275 %76:vreg_128 = GLOBAL_LOAD_DWORDX4 %72, 0, 0, 0, 0, implicit $exec
276 %77:vgpr_32 = IMPLICIT_DEF
277 %78:vgpr_32 = IMPLICIT_DEF
278 %79:vgpr_32 = V_MUL_F32_e32 0, %77, implicit $exec
279 %80:vgpr_32 = IMPLICIT_DEF
280 %81:vgpr_32 = IMPLICIT_DEF
281 %84:vgpr_32 = IMPLICIT_DEF
282 BUFFER_STORE_DWORD_OFFEN %84, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 108, 0, 0, 0, 0, 0, implicit $exec
283 BUFFER_STORE_DWORD_OFFEN %81, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 104, 0, 0, 0, 0, 0, implicit $exec
284 BUFFER_STORE_DWORD_OFFEN %80, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 100, 0, 0, 0, 0, 0, implicit $exec
285 BUFFER_STORE_DWORD_OFFEN %78, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 96, 0, 0, 0, 0, 0, implicit $exec
286 %85:vgpr_32 = IMPLICIT_DEF
287 %86:vgpr_32 = IMPLICIT_DEF
288 %87:vgpr_32 = IMPLICIT_DEF
289 %88:vgpr_32 = IMPLICIT_DEF
290 %90:vgpr_32 = IMPLICIT_DEF
291 %91:vgpr_32, dead %92:sreg_64 = V_DIV_SCALE_F32 %90, %90, 1065353216, implicit $exec
292 %95:vgpr_32 = V_FMA_F32 0, 0, 0, 0, 0, undef %93:vgpr_32, 0, 0, implicit $exec
293 %96:vgpr_32, %97:sreg_64 = V_DIV_SCALE_F32 1065353216, %90, 1065353216, implicit $exec
294 %98:vgpr_32 = IMPLICIT_DEF
295 %99:vgpr_32 = IMPLICIT_DEF
296 %100:vgpr_32 = IMPLICIT_DEF
297 %101:vgpr_32 = IMPLICIT_DEF
298 %102:vgpr_32 = IMPLICIT_DEF
299 %103:vgpr_32 = IMPLICIT_DEF
300 %104:vgpr_32 = IMPLICIT_DEF
301 %105:vgpr_32 = IMPLICIT_DEF
302 %106:vgpr_32, dead %107:sreg_64 = V_DIV_SCALE_F32 %90, %90, %105, implicit $exec
303 %108:vgpr_32 = V_RCP_F32_e32 0, implicit $exec
304 %109:vgpr_32 = IMPLICIT_DEF
305 %110:vgpr_32 = V_FMA_F32 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
306 %111:vgpr_32, %112:sreg_64 = V_DIV_SCALE_F32 0, 0, 0, implicit $exec
307 %113:vgpr_32 = V_MUL_F32_e32 0, %110, implicit $exec
308 %114:vgpr_32 = IMPLICIT_DEF
309 %115:vgpr_32 = IMPLICIT_DEF
310 %116:vgpr_32 = IMPLICIT_DEF
311 $vcc = IMPLICIT_DEF
312 %117:vgpr_32 = V_DIV_FMAS_F32 0, %116, 0, %110, 0, %115, 0, 0, implicit killed $vcc, implicit $exec
313 %118:vgpr_32 = V_DIV_FIXUP_F32 0, %117, 0, %90, 0, %105, 0, 0, implicit $exec
314 %119:vgpr_32 = IMPLICIT_DEF
315 %120:vgpr_32 = IMPLICIT_DEF
316 %121:vgpr_32 = IMPLICIT_DEF
317 %122:vgpr_32 = IMPLICIT_DEF
318 %123:vgpr_32 = IMPLICIT_DEF
319 %124:vgpr_32 = IMPLICIT_DEF
320 %125:vgpr_32 = IMPLICIT_DEF
321 %126:vgpr_32 = IMPLICIT_DEF
322 DBG_VALUE %103, _, !5, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !8
323 ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
324 %127:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc
325 $sgpr4 = COPY $sgpr101
326 $vgpr0 = COPY %124
327 $vgpr1_vgpr2 = IMPLICIT_DEF
328 $vgpr3 = COPY %126
329 dead $sgpr30_sgpr31 = SI_CALL %127, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit $vgpr0, implicit $vgpr1_vgpr2, implicit killed $vgpr3
330 ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
331 %128:vreg_64, dead %129:sreg_64 = V_MAD_I64_I32 %20, %34, 0, 0, implicit $exec
332 S_ENDPGM 0
334 ...