1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3 ; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator:
5 ; GCN: s_and_saveexec_b64
6 ; GCN: ; mask branch [[RET:BB[0-9]+_[0-9]+]]
8 ; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %unreachable
10 ; GCN: ; divergent unreachable
12 ; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock
15 define amdgpu_kernel void @lower_control_flow_unreachable_terminator() #0 {
17 %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
18 %tmp63 = icmp eq i32 %tmp15, 32
19 br i1 %tmp63, label %unreachable, label %ret
22 store volatile i32 0, i32 addrspace(3)* undef, align 4
29 ; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator_swap_block_order:
31 ; GCN: s_and_saveexec_b64
32 ; GCN: ; mask branch [[RETURN:BB[0-9]+_[0-9]+]]
34 ; GCN-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %unreachable
36 ; GCN: ; divergent unreachable
40 define amdgpu_kernel void @lower_control_flow_unreachable_terminator_swap_block_order() #0 {
42 %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
43 %tmp63 = icmp eq i32 %tmp15, 32
44 br i1 %tmp63, label %ret, label %unreachable
50 store volatile i32 0, i32 addrspace(3)* undef, align 4
54 ; GCN-LABEL: {{^}}uniform_lower_control_flow_unreachable_terminator:
56 ; GCN: s_cbranch_scc0 [[UNREACHABLE:BB[0-9]+_[0-9]+]]
58 ; GCN-NEXT: %bb.{{[0-9]+}}: ; %ret
61 ; GCN: [[UNREACHABLE]]:
63 define amdgpu_kernel void @uniform_lower_control_flow_unreachable_terminator(i32 %arg0) #0 {
65 %tmp63 = icmp eq i32 %arg0, 32
66 br i1 %tmp63, label %unreachable, label %ret
69 store volatile i32 0, i32 addrspace(3)* undef, align 4
76 declare i32 @llvm.amdgcn.workitem.id.y() #1
78 attributes #0 = { nounwind }
79 attributes #1 = { nounwind readnone }
80 attributes #2 = { nounwind }