1 ; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=HSA-TRAP %s
3 ; FIXME: merge with trap.ll
5 ; An s_cbranch_execnz is required to avoid trapping if all lanes are 0
6 ; GCN-LABEL: {{^}}trap_divergent_branch:
7 ; GCN: s_and_saveexec_b64
8 ; GCN: s_cbranch_execz [[ENDPGM:BB[0-9]+_[0-9]+]]
9 ; GCN: s_branch [[TRAP:BB[0-9]+_[0-9]+]]
15 define amdgpu_kernel void @trap_divergent_branch(i32 addrspace(1)* nocapture readonly %arg) {
16 %id = call i32 @llvm.amdgcn.workitem.id.x()
17 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
18 %divergent.val = load i32, i32 addrspace(1)* %gep
19 %cmp = icmp eq i32 %divergent.val, 0
20 br i1 %cmp, label %bb, label %end
23 call void @llvm.trap()
30 ; GCN-LABEL: {{^}}debugtrap_divergent_branch:
31 ; GCN: s_and_saveexec_b64
32 ; GCN: s_cbranch_execz [[ENDPGM:BB[0-9]+_[0-9]+]]
33 ; GCN: BB{{[0-9]+}}_{{[0-9]+}}:
35 ; GCN-NEXT: [[ENDPGM]]:
37 define amdgpu_kernel void @debugtrap_divergent_branch(i32 addrspace(1)* nocapture readonly %arg) {
38 %id = call i32 @llvm.amdgcn.workitem.id.x()
39 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
40 %divergent.val = load i32, i32 addrspace(1)* %gep
41 %cmp = icmp eq i32 %divergent.val, 0
42 br i1 %cmp, label %bb, label %end
45 call void @llvm.debugtrap()
52 declare void @llvm.trap() #0
53 declare void @llvm.debugtrap() #1
54 declare i32 @llvm.amdgcn.workitem.id.x() #2
56 attributes #0 = { nounwind noreturn }
57 attributes #1 = { nounwind }
58 attributes #2 = { nounwind readnone speculatable }