| blob | d61c1743114c3957ebd93ede643c713ca61dce6d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tahiti -mattr=-fp64-fp16-denormals -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,SI
3 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI
5 define amdgpu_kernel void @madak_f16(
6 ; SI-LABEL: madak_f16:
7 ; SI: ; %bb.0: ; %entry
8 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
10 ; SI-NEXT: s_mov_b32 s11, 0xf000
11 ; SI-NEXT: s_mov_b32 s10, -1
12 ; SI-NEXT: s_mov_b32 s2, s10
13 ; SI-NEXT: s_mov_b32 s3, s11
14 ; SI-NEXT: s_waitcnt lgkmcnt(0)
15 ; SI-NEXT: s_mov_b32 s12, s6
16 ; SI-NEXT: s_mov_b32 s13, s7
17 ; SI-NEXT: s_mov_b32 s14, s10
18 ; SI-NEXT: s_mov_b32 s15, s11
19 ; SI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
20 ; SI-NEXT: buffer_load_ushort v1, off, s[12:15], 0
21 ; SI-NEXT: s_mov_b32 s8, s4
22 ; SI-NEXT: s_mov_b32 s9, s5
23 ; SI-NEXT: s_waitcnt vmcnt(1)
24 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
25 ; SI-NEXT: s_waitcnt vmcnt(0)
26 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
27 ; SI-NEXT: v_madak_f32 v0, v1, v0, 0x41200000
28 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
29 ; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
30 ; SI-NEXT: s_endpgm
31 ;
32 ; VI-LABEL: madak_f16:
33 ; VI: ; %bb.0: ; %entry
34 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
35 ; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
36 ; VI-NEXT: s_mov_b32 s3, 0xf000
37 ; VI-NEXT: s_mov_b32 s2, -1
38 ; VI-NEXT: s_mov_b32 s10, s2
39 ; VI-NEXT: s_waitcnt lgkmcnt(0)
40 ; VI-NEXT: s_mov_b32 s0, s4
41 ; VI-NEXT: s_mov_b32 s1, s5
42 ; VI-NEXT: s_mov_b32 s4, s6
43 ; VI-NEXT: s_mov_b32 s5, s7
44 ; VI-NEXT: s_mov_b32 s11, s3
45 ; VI-NEXT: s_mov_b32 s6, s2
46 ; VI-NEXT: s_mov_b32 s7, s3
47 ; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
48 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
49 ; VI-NEXT: s_waitcnt vmcnt(0)
50 ; VI-NEXT: v_madak_f16 v0, v0, v1, 0x4900
51 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
52 ; VI-NEXT: s_endpgm
53 half addrspace(1)* %r,
54 half addrspace(1)* %a,
55 half addrspace(1)* %b) {
56 entry:
57 %a.val = load half, half addrspace(1)* %a
58 %b.val = load half, half addrspace(1)* %b
60 %t.val = fmul half %a.val, %b.val
61 %r.val = fadd half %t.val, 10.0
63 store half %r.val, half addrspace(1)* %r
64 ret void
65 }
67 define amdgpu_kernel void @madak_f16_use_2(
68 ; SI-LABEL: madak_f16_use_2:
69 ; SI: ; %bb.0: ; %entry
70 ; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
71 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
72 ; SI-NEXT: s_mov_b32 s15, 0xf000
73 ; SI-NEXT: s_mov_b32 s14, -1
74 ; SI-NEXT: s_mov_b32 s2, s14
75 ; SI-NEXT: s_waitcnt lgkmcnt(0)
76 ; SI-NEXT: s_mov_b32 s16, s10
77 ; SI-NEXT: s_mov_b32 s17, s11
78 ; SI-NEXT: s_mov_b32 s3, s15
79 ; SI-NEXT: s_mov_b32 s18, s14
80 ; SI-NEXT: s_mov_b32 s19, s15
81 ; SI-NEXT: s_mov_b32 s10, s14
82 ; SI-NEXT: s_mov_b32 s11, s15
83 ; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
84 ; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0
85 ; SI-NEXT: buffer_load_ushort v2, off, s[0:3], 0
86 ; SI-NEXT: v_mov_b32_e32 v3, 0x41200000
87 ; SI-NEXT: s_mov_b32 s12, s6
88 ; SI-NEXT: s_mov_b32 s13, s7
89 ; SI-NEXT: s_mov_b32 s6, s14
90 ; SI-NEXT: s_mov_b32 s7, s15
91 ; SI-NEXT: s_waitcnt vmcnt(2)
92 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
93 ; SI-NEXT: s_waitcnt vmcnt(1)
94 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
95 ; SI-NEXT: s_waitcnt vmcnt(0)
96 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
97 ; SI-NEXT: v_madak_f32 v1, v0, v1, 0x41200000
98 ; SI-NEXT: v_mac_f32_e32 v3, v0, v2
99 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
100 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
101 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
102 ; SI-NEXT: buffer_store_short v1, off, s[12:15], 0
103 ; SI-NEXT: s_endpgm
104 ;
105 ; VI-LABEL: madak_f16_use_2:
106 ; VI: ; %bb.0: ; %entry
107 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
108 ; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
109 ; VI-NEXT: s_mov_b32 s3, 0xf000
110 ; VI-NEXT: s_mov_b32 s2, -1
111 ; VI-NEXT: s_mov_b32 s14, s2
112 ; VI-NEXT: s_waitcnt lgkmcnt(0)
113 ; VI-NEXT: s_mov_b32 s16, s10
114 ; VI-NEXT: s_mov_b32 s17, s11
115 ; VI-NEXT: s_mov_b32 s15, s3
116 ; VI-NEXT: s_mov_b32 s18, s2
117 ; VI-NEXT: s_mov_b32 s19, s3
118 ; VI-NEXT: s_mov_b32 s10, s2
119 ; VI-NEXT: s_mov_b32 s11, s3
120 ; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
121 ; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0
122 ; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0
123 ; VI-NEXT: v_mov_b32_e32 v2, 0x4900
124 ; VI-NEXT: s_mov_b32 s0, s6
125 ; VI-NEXT: s_mov_b32 s1, s7
126 ; VI-NEXT: s_mov_b32 s6, s2
127 ; VI-NEXT: s_mov_b32 s7, s3
128 ; VI-NEXT: s_waitcnt vmcnt(1)
129 ; VI-NEXT: v_madak_f16 v1, v0, v1, 0x4900
130 ; VI-NEXT: s_waitcnt vmcnt(0)
131 ; VI-NEXT: v_mac_f16_e32 v2, v0, v3
132 ; VI-NEXT: buffer_store_short v1, off, s[4:7], 0
133 ; VI-NEXT: buffer_store_short v2, off, s[0:3], 0
134 ; VI-NEXT: s_endpgm
135 half addrspace(1)* %r0,
136 half addrspace(1)* %r1,
137 half addrspace(1)* %a,
138 half addrspace(1)* %b,
139 half addrspace(1)* %c) {
140 entry:
141 %a.val = load volatile half, half addrspace(1)* %a
142 %b.val = load volatile half, half addrspace(1)* %b
143 %c.val = load volatile half, half addrspace(1)* %c
145 %t0.val = fmul half %a.val, %b.val
146 %t1.val = fmul half %a.val, %c.val
147 %r0.val = fadd half %t0.val, 10.0
148 %r1.val = fadd half %t1.val, 10.0
150 store half %r0.val, half addrspace(1)* %r0
151 store half %r1.val, half addrspace(1)* %r1
152 ret void
153 }