1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
3 ; RUN: llc -march=amdgcn --misched=ilpmax -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
4 ; RUN: llc -march=amdgcn --misched=ilpmax -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
5 ; The ilpmax scheduler is used for the second test to get the ordering we want for the test.
7 ; DEFAULT-LABEL: {{^}}main:
8 ; DEFAULT: s_load_dwordx4
9 ; DEFAULT: s_load_dwordx4
10 ; DEFAULT: s_waitcnt lgkmcnt(0)
11 ; DEFAULT: buffer_load_format_xyzw
12 ; DEFAULT: s_waitcnt vmcnt(0)
13 ; DEFAULT: buffer_load_format_xyzw
14 ; DEFAULT: s_waitcnt vmcnt(0)
17 ; DEFAULT-NEXT: s_endpgm
18 define amdgpu_vs void @main(<16 x i8> addrspace(4)* inreg %arg, <16 x i8> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, <16 x i8> addrspace(4)* inreg %arg3, <16 x i8> addrspace(4)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(4)* inreg %constptr) #0 {
20 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(4)* %arg3, i32 0
21 %tmp10 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp, !tbaa !0
22 %tmp10.cast = bitcast <16 x i8> %tmp10 to <4 x i32>
23 %tmp11 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp10.cast, i32 %arg6, i32 0, i1 false, i1 false)
24 %tmp12 = extractelement <4 x float> %tmp11, i32 0
25 %tmp13 = extractelement <4 x float> %tmp11, i32 1
26 call void @llvm.amdgcn.s.barrier() #1
27 %tmp14 = extractelement <4 x float> %tmp11, i32 2
28 %tmp15 = load float, float addrspace(4)* %constptr, align 4
29 %tmp16 = getelementptr <16 x i8>, <16 x i8> addrspace(4)* %arg3, i32 1
30 %tmp17 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp16, !tbaa !0
31 %tmp17.cast = bitcast <16 x i8> %tmp17 to <4 x i32>
32 %tmp18 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp17.cast, i32 %arg6, i32 0, i1 false, i1 false)
33 %tmp19 = extractelement <4 x float> %tmp18, i32 0
34 %tmp20 = extractelement <4 x float> %tmp18, i32 1
35 %tmp21 = extractelement <4 x float> %tmp18, i32 2
36 %tmp22 = extractelement <4 x float> %tmp18, i32 3
37 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %tmp19, float %tmp20, float %tmp21, float %tmp22, i1 false, i1 false) #0
38 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp12, float %tmp13, float %tmp14, float %tmp15, i1 true, i1 false) #0
42 ; ILPMAX-LABEL: {{^}}main2:
43 ; ILPMAX: s_load_dwordx4
44 ; ILPMAX: s_waitcnt lgkmcnt(0)
46 ; ILPMAX: s_load_dwordx4
47 ; ILPMAX: s_waitcnt lgkmcnt(0)
49 ; ILPMAX: s_waitcnt vmcnt(0)
51 ; ILPMAX-NEXT: exp param0
53 define amdgpu_vs void @main2([6 x <16 x i8>] addrspace(4)* inreg %arg, [17 x <16 x i8>] addrspace(4)* inreg %arg1, [17 x <4 x i32>] addrspace(4)* inreg %arg2, [34 x <8 x i32>] addrspace(4)* inreg %arg3, [16 x <16 x i8>] addrspace(4)* inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
55 %tmp = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(4)* %arg4, i64 0, i64 0
56 %tmp11 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp, align 16, !tbaa !0
57 %tmp12 = add i32 %arg5, %arg7
58 %tmp11.cast = bitcast <16 x i8> %tmp11 to <4 x i32>
59 %tmp13 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp11.cast, i32 %tmp12, i32 0, i1 false, i1 false)
60 %tmp14 = extractelement <4 x float> %tmp13, i32 0
61 %tmp15 = extractelement <4 x float> %tmp13, i32 1
62 %tmp16 = extractelement <4 x float> %tmp13, i32 2
63 %tmp17 = extractelement <4 x float> %tmp13, i32 3
64 %tmp18 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(4)* %arg4, i64 0, i64 1
65 %tmp19 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp18, align 16, !tbaa !0
66 %tmp20 = add i32 %arg5, %arg7
67 %tmp19.cast = bitcast <16 x i8> %tmp19 to <4 x i32>
68 %tmp21 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp19.cast, i32 %tmp20, i32 0, i1 false, i1 false)
69 %tmp22 = extractelement <4 x float> %tmp21, i32 0
70 %tmp23 = extractelement <4 x float> %tmp21, i32 1
71 %tmp24 = extractelement <4 x float> %tmp21, i32 2
72 %tmp25 = extractelement <4 x float> %tmp21, i32 3
73 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp14, float %tmp15, float %tmp16, float %tmp17, i1 false, i1 false) #0
74 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %tmp22, float %tmp23, float %tmp24, float %tmp25, i1 true, i1 false) #0
78 declare void @llvm.amdgcn.s.barrier() #1
79 declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2
80 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
82 attributes #0 = { nounwind }
83 attributes #1 = { convergent nounwind }
84 attributes #2 = { nounwind readonly }
86 !0 = !{!1, !1, i64 0, i32 1}