| blob | 4beebc0b34a2681ff9ab3c3b0879fce131e1305d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
3 ; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
5 define amdgpu_kernel void @widen_i16_constant_load(i16 addrspace(4)* %arg) {
6 ; SI-LABEL: widen_i16_constant_load:
7 ; SI: ; %bb.0:
8 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
9 ; SI-NEXT: s_mov_b32 s5, 0
10 ; SI-NEXT: s_mov_b32 s4, 0
11 ; SI-NEXT: s_mov_b32 s7, 0xf000
12 ; SI-NEXT: s_mov_b32 s6, -1
13 ; SI-NEXT: s_waitcnt lgkmcnt(0)
14 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
15 ; SI-NEXT: s_waitcnt lgkmcnt(0)
16 ; SI-NEXT: s_addk_i32 s0, 0x3e7
17 ; SI-NEXT: s_or_b32 s0, s0, 4
18 ; SI-NEXT: v_mov_b32_e32 v0, s0
19 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
20 ; SI-NEXT: s_endpgm
21 ;
22 ; VI-LABEL: widen_i16_constant_load:
23 ; VI: ; %bb.0:
24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
25 ; VI-NEXT: v_mov_b32_e32 v0, 0
26 ; VI-NEXT: v_mov_b32_e32 v1, 0
27 ; VI-NEXT: s_waitcnt lgkmcnt(0)
28 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
29 ; VI-NEXT: s_waitcnt lgkmcnt(0)
30 ; VI-NEXT: s_addk_i32 s0, 0x3e7
31 ; VI-NEXT: s_or_b32 s0, s0, 4
32 ; VI-NEXT: v_mov_b32_e32 v2, s0
33 ; VI-NEXT: flat_store_short v[0:1], v2
34 ; VI-NEXT: s_endpgm
35 %load = load i16, i16 addrspace(4)* %arg, align 4
36 %add = add i16 %load, 999
37 %or = or i16 %add, 4
38 store i16 %or, i16 addrspace(1)* null
39 ret void
40 }
42 define amdgpu_kernel void @widen_i16_constant_load_zext_i32(i16 addrspace(4)* %arg) {
43 ; SI-LABEL: widen_i16_constant_load_zext_i32:
44 ; SI: ; %bb.0:
45 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
46 ; SI-NEXT: s_mov_b32 s5, 0
47 ; SI-NEXT: s_mov_b32 s4, 0
48 ; SI-NEXT: s_mov_b32 s7, 0xf000
49 ; SI-NEXT: s_mov_b32 s6, -1
50 ; SI-NEXT: s_waitcnt lgkmcnt(0)
51 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
52 ; SI-NEXT: s_waitcnt lgkmcnt(0)
53 ; SI-NEXT: s_and_b32 s0, s0, 0xffff
54 ; SI-NEXT: s_addk_i32 s0, 0x3e7
55 ; SI-NEXT: s_or_b32 s0, s0, 4
56 ; SI-NEXT: v_mov_b32_e32 v0, s0
57 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
58 ; SI-NEXT: s_endpgm
59 ;
60 ; VI-LABEL: widen_i16_constant_load_zext_i32:
61 ; VI: ; %bb.0:
62 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
63 ; VI-NEXT: v_mov_b32_e32 v0, 0
64 ; VI-NEXT: v_mov_b32_e32 v1, 0
65 ; VI-NEXT: s_waitcnt lgkmcnt(0)
66 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
67 ; VI-NEXT: s_waitcnt lgkmcnt(0)
68 ; VI-NEXT: s_and_b32 s0, s0, 0xffff
69 ; VI-NEXT: s_addk_i32 s0, 0x3e7
70 ; VI-NEXT: s_or_b32 s0, s0, 4
71 ; VI-NEXT: v_mov_b32_e32 v2, s0
72 ; VI-NEXT: flat_store_dword v[0:1], v2
73 ; VI-NEXT: s_endpgm
74 %load = load i16, i16 addrspace(4)* %arg, align 4
75 %ext = zext i16 %load to i32
76 %add = add i32 %ext, 999
77 %or = or i32 %add, 4
78 store i32 %or, i32 addrspace(1)* null
79 ret void
80 }
82 define amdgpu_kernel void @widen_i16_constant_load_sext_i32(i16 addrspace(4)* %arg) {
83 ; SI-LABEL: widen_i16_constant_load_sext_i32:
84 ; SI: ; %bb.0:
85 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
86 ; SI-NEXT: s_mov_b32 s5, 0
87 ; SI-NEXT: s_mov_b32 s4, 0
88 ; SI-NEXT: s_mov_b32 s7, 0xf000
89 ; SI-NEXT: s_mov_b32 s6, -1
90 ; SI-NEXT: s_waitcnt lgkmcnt(0)
91 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
92 ; SI-NEXT: s_waitcnt lgkmcnt(0)
93 ; SI-NEXT: s_sext_i32_i16 s0, s0
94 ; SI-NEXT: s_addk_i32 s0, 0x3e7
95 ; SI-NEXT: s_or_b32 s0, s0, 4
96 ; SI-NEXT: v_mov_b32_e32 v0, s0
97 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
98 ; SI-NEXT: s_endpgm
99 ;
100 ; VI-LABEL: widen_i16_constant_load_sext_i32:
101 ; VI: ; %bb.0:
102 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
103 ; VI-NEXT: v_mov_b32_e32 v0, 0
104 ; VI-NEXT: v_mov_b32_e32 v1, 0
105 ; VI-NEXT: s_waitcnt lgkmcnt(0)
106 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
107 ; VI-NEXT: s_waitcnt lgkmcnt(0)
108 ; VI-NEXT: s_sext_i32_i16 s0, s0
109 ; VI-NEXT: s_addk_i32 s0, 0x3e7
110 ; VI-NEXT: s_or_b32 s0, s0, 4
111 ; VI-NEXT: v_mov_b32_e32 v2, s0
112 ; VI-NEXT: flat_store_dword v[0:1], v2
113 ; VI-NEXT: s_endpgm
114 %load = load i16, i16 addrspace(4)* %arg, align 4
115 %ext = sext i16 %load to i32
116 %add = add i32 %ext, 999
117 %or = or i32 %add, 4
118 store i32 %or, i32 addrspace(1)* null
119 ret void
120 }
122 define amdgpu_kernel void @widen_i17_constant_load(i17 addrspace(4)* %arg) {
123 ; SI-LABEL: widen_i17_constant_load:
124 ; SI: ; %bb.0:
125 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
126 ; SI-NEXT: s_mov_b32 s5, 0
127 ; SI-NEXT: s_mov_b32 s4, 0
128 ; SI-NEXT: s_mov_b32 s7, 0xf000
129 ; SI-NEXT: s_mov_b32 s6, -1
130 ; SI-NEXT: s_waitcnt lgkmcnt(0)
131 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
132 ; SI-NEXT: s_waitcnt lgkmcnt(0)
133 ; SI-NEXT: s_add_i32 s0, s0, 34
134 ; SI-NEXT: s_or_b32 s0, s0, 4
135 ; SI-NEXT: v_mov_b32_e32 v0, s0
136 ; SI-NEXT: s_bfe_u32 s0, s0, 0x10010
137 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
138 ; SI-NEXT: s_mov_b32 s4, 2
139 ; SI-NEXT: s_waitcnt expcnt(0)
140 ; SI-NEXT: v_mov_b32_e32 v0, s0
141 ; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
142 ; SI-NEXT: s_endpgm
143 ;
144 ; VI-LABEL: widen_i17_constant_load:
145 ; VI: ; %bb.0:
146 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
147 ; VI-NEXT: v_mov_b32_e32 v0, 0
148 ; VI-NEXT: v_mov_b32_e32 v2, 2
149 ; VI-NEXT: v_mov_b32_e32 v1, 0
150 ; VI-NEXT: v_mov_b32_e32 v3, 0
151 ; VI-NEXT: s_waitcnt lgkmcnt(0)
152 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
153 ; VI-NEXT: s_waitcnt lgkmcnt(0)
154 ; VI-NEXT: s_add_i32 s0, s0, 34
155 ; VI-NEXT: s_or_b32 s0, s0, 4
156 ; VI-NEXT: v_mov_b32_e32 v4, s0
157 ; VI-NEXT: s_bfe_u32 s0, s0, 0x10010
158 ; VI-NEXT: v_mov_b32_e32 v5, s0
159 ; VI-NEXT: flat_store_short v[0:1], v4
160 ; VI-NEXT: flat_store_byte v[2:3], v5
161 ; VI-NEXT: s_endpgm
162 %load = load i17, i17 addrspace(4)* %arg, align 4
163 %add = add i17 %load, 34
164 %or = or i17 %add, 4
165 store i17 %or, i17 addrspace(1)* null
166 ret void
167 }
169 define amdgpu_kernel void @widen_f16_constant_load(half addrspace(4)* %arg) {
170 ; SI-LABEL: widen_f16_constant_load:
171 ; SI: ; %bb.0:
172 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
173 ; SI-NEXT: s_mov_b32 s3, 0xf000
174 ; SI-NEXT: s_mov_b32 s2, -1
175 ; SI-NEXT: s_waitcnt lgkmcnt(0)
176 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
177 ; SI-NEXT: s_mov_b32 s1, 0
178 ; SI-NEXT: s_waitcnt lgkmcnt(0)
179 ; SI-NEXT: v_cvt_f32_f16_e32 v0, s0
180 ; SI-NEXT: s_mov_b32 s0, 0
181 ; SI-NEXT: v_add_f32_e32 v0, 4.0, v0
182 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
183 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
184 ; SI-NEXT: s_endpgm
185 ;
186 ; VI-LABEL: widen_f16_constant_load:
187 ; VI: ; %bb.0:
188 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
189 ; VI-NEXT: v_mov_b32_e32 v0, 0
190 ; VI-NEXT: v_mov_b32_e32 v1, 0
191 ; VI-NEXT: s_waitcnt lgkmcnt(0)
192 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
193 ; VI-NEXT: s_waitcnt lgkmcnt(0)
194 ; VI-NEXT: v_add_f16_e64 v2, s0, 4.0
195 ; VI-NEXT: flat_store_short v[0:1], v2
196 ; VI-NEXT: s_endpgm
197 %load = load half, half addrspace(4)* %arg, align 4
198 %add = fadd half %load, 4.0
199 store half %add, half addrspace(1)* null
200 ret void
201 }
203 ; FIXME: valu usage on VI
204 define amdgpu_kernel void @widen_v2i8_constant_load(<2 x i8> addrspace(4)* %arg) {
205 ; SI-LABEL: widen_v2i8_constant_load:
206 ; SI: ; %bb.0:
207 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
208 ; SI-NEXT: s_mov_b32 s5, 0
209 ; SI-NEXT: s_mov_b32 s4, 0
210 ; SI-NEXT: s_mov_b32 s7, 0xf000
211 ; SI-NEXT: s_mov_b32 s6, -1
212 ; SI-NEXT: s_waitcnt lgkmcnt(0)
213 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
214 ; SI-NEXT: s_waitcnt lgkmcnt(0)
215 ; SI-NEXT: s_and_b32 s1, s0, 0xff00
216 ; SI-NEXT: s_add_i32 s0, s0, 12
217 ; SI-NEXT: s_or_b32 s0, s0, 4
218 ; SI-NEXT: s_and_b32 s0, s0, 0xff
219 ; SI-NEXT: s_or_b32 s0, s1, s0
220 ; SI-NEXT: s_addk_i32 s0, 0x2c00
221 ; SI-NEXT: s_or_b32 s0, s0, 0x300
222 ; SI-NEXT: v_mov_b32_e32 v0, s0
223 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
224 ; SI-NEXT: s_endpgm
225 ;
226 ; VI-LABEL: widen_v2i8_constant_load:
227 ; VI: ; %bb.0:
228 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
229 ; VI-NEXT: v_mov_b32_e32 v0, 44
230 ; VI-NEXT: v_mov_b32_e32 v1, 3
231 ; VI-NEXT: s_waitcnt lgkmcnt(0)
232 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
233 ; VI-NEXT: s_waitcnt lgkmcnt(0)
234 ; VI-NEXT: s_and_b32 s1, s0, 0xffff
235 ; VI-NEXT: v_mov_b32_e32 v2, s0
236 ; VI-NEXT: s_add_i32 s1, s1, 12
237 ; VI-NEXT: v_add_u32_sdwa v0, vcc, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
238 ; VI-NEXT: s_or_b32 s0, s1, 4
239 ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
240 ; VI-NEXT: s_and_b32 s0, s0, 0xff
241 ; VI-NEXT: v_or_b32_e32 v2, s0, v0
242 ; VI-NEXT: v_mov_b32_e32 v0, 0
243 ; VI-NEXT: v_mov_b32_e32 v1, 0
244 ; VI-NEXT: flat_store_short v[0:1], v2
245 ; VI-NEXT: s_endpgm
246 %load = load <2 x i8>, <2 x i8> addrspace(4)* %arg, align 4
247 %add = add <2 x i8> %load, <i8 12, i8 44>
248 %or = or <2 x i8> %add, <i8 4, i8 3>
249 store <2 x i8> %or, <2 x i8> addrspace(1)* null
250 ret void
251 }
253 define amdgpu_kernel void @no_widen_i16_constant_divergent_load(i16 addrspace(4)* %arg) {
254 ; SI-LABEL: no_widen_i16_constant_divergent_load:
255 ; SI: ; %bb.0:
256 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
257 ; SI-NEXT: s_mov_b32 s2, 0
258 ; SI-NEXT: s_mov_b32 s3, 0xf000
259 ; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
260 ; SI-NEXT: v_mov_b32_e32 v1, 0
261 ; SI-NEXT: s_waitcnt lgkmcnt(0)
262 ; SI-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64
263 ; SI-NEXT: s_mov_b32 s1, 0
264 ; SI-NEXT: s_mov_b32 s0, 0
265 ; SI-NEXT: s_mov_b32 s2, -1
266 ; SI-NEXT: s_waitcnt vmcnt(0)
267 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3e7, v0
268 ; SI-NEXT: v_or_b32_e32 v0, 4, v0
269 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
270 ; SI-NEXT: s_endpgm
271 ;
272 ; VI-LABEL: no_widen_i16_constant_divergent_load:
273 ; VI: ; %bb.0:
274 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
275 ; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
276 ; VI-NEXT: v_mov_b32_e32 v0, 0
277 ; VI-NEXT: v_mov_b32_e32 v1, 0
278 ; VI-NEXT: s_waitcnt lgkmcnt(0)
279 ; VI-NEXT: v_mov_b32_e32 v3, s1
280 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
281 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
282 ; VI-NEXT: flat_load_ushort v2, v[2:3]
283 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
284 ; VI-NEXT: v_add_u16_e32 v2, 0x3e7, v2
285 ; VI-NEXT: v_or_b32_e32 v2, 4, v2
286 ; VI-NEXT: flat_store_short v[0:1], v2
287 ; VI-NEXT: s_endpgm
288 %tid = call i32 @llvm.amdgcn.workitem.id.x()
289 %tid.ext = zext i32 %tid to i64
290 %gep.arg = getelementptr inbounds i16, i16 addrspace(4)* %arg, i64 %tid.ext
291 %load = load i16, i16 addrspace(4)* %gep.arg, align 4
292 %add = add i16 %load, 999
293 %or = or i16 %add, 4
294 store i16 %or, i16 addrspace(1)* null
295 ret void
296 }
298 define amdgpu_kernel void @widen_i1_constant_load(i1 addrspace(4)* %arg) {
299 ; SI-LABEL: widen_i1_constant_load:
300 ; SI: ; %bb.0:
301 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
302 ; SI-NEXT: s_mov_b32 s5, 0
303 ; SI-NEXT: s_mov_b32 s4, 0
304 ; SI-NEXT: s_mov_b32 s7, 0xf000
305 ; SI-NEXT: s_mov_b32 s6, -1
306 ; SI-NEXT: s_waitcnt lgkmcnt(0)
307 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
308 ; SI-NEXT: s_waitcnt lgkmcnt(0)
309 ; SI-NEXT: s_and_b32 s0, s0, 1
310 ; SI-NEXT: v_mov_b32_e32 v0, s0
311 ; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
312 ; SI-NEXT: s_endpgm
313 ;
314 ; VI-LABEL: widen_i1_constant_load:
315 ; VI: ; %bb.0:
316 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
317 ; VI-NEXT: v_mov_b32_e32 v0, 0
318 ; VI-NEXT: v_mov_b32_e32 v1, 0
319 ; VI-NEXT: s_waitcnt lgkmcnt(0)
320 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
321 ; VI-NEXT: s_waitcnt lgkmcnt(0)
322 ; VI-NEXT: s_and_b32 s0, s0, 1
323 ; VI-NEXT: v_mov_b32_e32 v2, s0
324 ; VI-NEXT: flat_store_byte v[0:1], v2
325 ; VI-NEXT: s_endpgm
326 %load = load i1, i1 addrspace(4)* %arg, align 4
327 %and = and i1 %load, true
328 store i1 %and, i1 addrspace(1)* null
329 ret void
330 }
332 define amdgpu_kernel void @widen_i16_zextload_i64_constant_load(i16 addrspace(4)* %arg) {
333 ; SI-LABEL: widen_i16_zextload_i64_constant_load:
334 ; SI: ; %bb.0:
335 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
336 ; SI-NEXT: s_mov_b32 s5, 0
337 ; SI-NEXT: s_mov_b32 s4, 0
338 ; SI-NEXT: s_mov_b32 s7, 0xf000
339 ; SI-NEXT: s_mov_b32 s6, -1
340 ; SI-NEXT: s_waitcnt lgkmcnt(0)
341 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
342 ; SI-NEXT: s_waitcnt lgkmcnt(0)
343 ; SI-NEXT: s_and_b32 s0, s0, 0xffff
344 ; SI-NEXT: s_addk_i32 s0, 0x3e7
345 ; SI-NEXT: s_or_b32 s0, s0, 4
346 ; SI-NEXT: v_mov_b32_e32 v0, s0
347 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
348 ; SI-NEXT: s_endpgm
349 ;
350 ; VI-LABEL: widen_i16_zextload_i64_constant_load:
351 ; VI: ; %bb.0:
352 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
353 ; VI-NEXT: v_mov_b32_e32 v0, 0
354 ; VI-NEXT: v_mov_b32_e32 v1, 0
355 ; VI-NEXT: s_waitcnt lgkmcnt(0)
356 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
357 ; VI-NEXT: s_waitcnt lgkmcnt(0)
358 ; VI-NEXT: s_and_b32 s0, s0, 0xffff
359 ; VI-NEXT: s_addk_i32 s0, 0x3e7
360 ; VI-NEXT: s_or_b32 s0, s0, 4
361 ; VI-NEXT: v_mov_b32_e32 v2, s0
362 ; VI-NEXT: flat_store_dword v[0:1], v2
363 ; VI-NEXT: s_endpgm
364 %load = load i16, i16 addrspace(4)* %arg, align 4
365 %zext = zext i16 %load to i32
366 %add = add i32 %zext, 999
367 %or = or i32 %add, 4
368 store i32 %or, i32 addrspace(1)* null
369 ret void
370 }
372 define amdgpu_kernel void @widen_i1_zext_to_i64_constant_load(i1 addrspace(4)* %arg) {
373 ; SI-LABEL: widen_i1_zext_to_i64_constant_load:
374 ; SI: ; %bb.0:
375 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
376 ; SI-NEXT: s_mov_b32 s5, 0
377 ; SI-NEXT: s_mov_b32 s4, 0
378 ; SI-NEXT: s_mov_b32 s7, 0xf000
379 ; SI-NEXT: s_mov_b32 s6, -1
380 ; SI-NEXT: s_waitcnt lgkmcnt(0)
381 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
382 ; SI-NEXT: s_waitcnt lgkmcnt(0)
383 ; SI-NEXT: s_and_b32 s0, s0, 1
384 ; SI-NEXT: s_add_u32 s0, s0, 0x3e7
385 ; SI-NEXT: s_addc_u32 s1, 0, 0
386 ; SI-NEXT: v_mov_b32_e32 v0, s0
387 ; SI-NEXT: v_mov_b32_e32 v1, s1
388 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
389 ; SI-NEXT: s_endpgm
390 ;
391 ; VI-LABEL: widen_i1_zext_to_i64_constant_load:
392 ; VI: ; %bb.0:
393 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
394 ; VI-NEXT: v_mov_b32_e32 v0, 0
395 ; VI-NEXT: v_mov_b32_e32 v1, 0
396 ; VI-NEXT: s_waitcnt lgkmcnt(0)
397 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
398 ; VI-NEXT: s_waitcnt lgkmcnt(0)
399 ; VI-NEXT: s_and_b32 s0, s0, 1
400 ; VI-NEXT: s_add_u32 s0, s0, 0x3e7
401 ; VI-NEXT: s_addc_u32 s1, 0, 0
402 ; VI-NEXT: v_mov_b32_e32 v3, s1
403 ; VI-NEXT: v_mov_b32_e32 v2, s0
404 ; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
405 ; VI-NEXT: s_endpgm
406 %load = load i1, i1 addrspace(4)* %arg, align 4
407 %zext = zext i1 %load to i64
408 %add = add i64 %zext, 999
409 store i64 %add, i64 addrspace(1)* null
410 ret void
411 }
413 define amdgpu_kernel void @widen_i16_constant32_load(i16 addrspace(6)* %arg) {
414 ; SI-LABEL: widen_i16_constant32_load:
415 ; SI: ; %bb.0:
416 ; SI-NEXT: s_load_dword s0, s[0:1], 0x9
417 ; SI-NEXT: s_mov_b32 s1, 0
418 ; SI-NEXT: s_mov_b32 s5, 0
419 ; SI-NEXT: s_mov_b32 s4, 0
420 ; SI-NEXT: s_mov_b32 s7, 0xf000
421 ; SI-NEXT: s_waitcnt lgkmcnt(0)
422 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
423 ; SI-NEXT: s_mov_b32 s6, -1
424 ; SI-NEXT: s_waitcnt lgkmcnt(0)
425 ; SI-NEXT: s_addk_i32 s0, 0x3e7
426 ; SI-NEXT: s_or_b32 s0, s0, 4
427 ; SI-NEXT: v_mov_b32_e32 v0, s0
428 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
429 ; SI-NEXT: s_endpgm
430 ;
431 ; VI-LABEL: widen_i16_constant32_load:
432 ; VI: ; %bb.0:
433 ; VI-NEXT: s_load_dword s0, s[0:1], 0x24
434 ; VI-NEXT: s_mov_b32 s1, 0
435 ; VI-NEXT: v_mov_b32_e32 v0, 0
436 ; VI-NEXT: v_mov_b32_e32 v1, 0
437 ; VI-NEXT: s_waitcnt lgkmcnt(0)
438 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
439 ; VI-NEXT: s_waitcnt lgkmcnt(0)
440 ; VI-NEXT: s_addk_i32 s0, 0x3e7
441 ; VI-NEXT: s_or_b32 s0, s0, 4
442 ; VI-NEXT: v_mov_b32_e32 v2, s0
443 ; VI-NEXT: flat_store_short v[0:1], v2
444 ; VI-NEXT: s_endpgm
445 %load = load i16, i16 addrspace(6)* %arg, align 4
446 %add = add i16 %load, 999
447 %or = or i16 %add, 4
448 store i16 %or, i16 addrspace(1)* null
449 ret void
450 }
452 define amdgpu_kernel void @widen_i16_global_invariant_load(i16 addrspace(1)* %arg) {
453 ; SI-LABEL: widen_i16_global_invariant_load:
454 ; SI: ; %bb.0:
455 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
456 ; SI-NEXT: s_mov_b32 s5, 0
457 ; SI-NEXT: s_mov_b32 s4, 0
458 ; SI-NEXT: s_mov_b32 s7, 0xf000
459 ; SI-NEXT: s_mov_b32 s6, -1
460 ; SI-NEXT: s_waitcnt lgkmcnt(0)
461 ; SI-NEXT: s_load_dword s0, s[0:1], 0x0
462 ; SI-NEXT: s_waitcnt lgkmcnt(0)
463 ; SI-NEXT: s_addk_i32 s0, 0x3e7
464 ; SI-NEXT: s_or_b32 s0, s0, 1
465 ; SI-NEXT: v_mov_b32_e32 v0, s0
466 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
467 ; SI-NEXT: s_endpgm
468 ;
469 ; VI-LABEL: widen_i16_global_invariant_load:
470 ; VI: ; %bb.0:
471 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
472 ; VI-NEXT: v_mov_b32_e32 v0, 0
473 ; VI-NEXT: v_mov_b32_e32 v1, 0
474 ; VI-NEXT: s_waitcnt lgkmcnt(0)
475 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
476 ; VI-NEXT: s_waitcnt lgkmcnt(0)
477 ; VI-NEXT: s_addk_i32 s0, 0x3e7
478 ; VI-NEXT: s_or_b32 s0, s0, 1
479 ; VI-NEXT: v_mov_b32_e32 v2, s0
480 ; VI-NEXT: flat_store_short v[0:1], v2
481 ; VI-NEXT: s_endpgm
482 %load = load i16, i16 addrspace(1)* %arg, align 4, !invariant.load !0
483 %add = add i16 %load, 999
484 %or = or i16 %add, 1
485 store i16 %or, i16 addrspace(1)* null
486 ret void
487 }
489 declare i32 @llvm.amdgcn.workitem.id.x()
491 !0 = !{}