1 ; RUN: llc -march=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %s | FileCheck %s
3 declare void @llvm.write_register.i32(metadata, i32) #0
4 declare void @llvm.write_register.i64(metadata, i64) #0
6 ; CHECK-LABEL: {{^}}test_write_m0:
7 define amdgpu_kernel void @test_write_m0(i32 %val) #0 {
8 call void @llvm.write_register.i32(metadata !0, i32 0)
9 call void @llvm.write_register.i32(metadata !0, i32 -1)
10 call void @llvm.write_register.i32(metadata !0, i32 %val)
11 call void @llvm.amdgcn.wave.barrier() #1
15 ; CHECK-LABEL: {{^}}test_write_exec:
16 ; CHECK: s_mov_b64 exec, 0
17 ; CHECK: s_mov_b64 exec, -1
18 ; CHECK: s_mov_b64 exec, s{{\[[0-9]+:[0-9]+\]}}
19 define amdgpu_kernel void @test_write_exec(i64 %val) #0 {
20 call void @llvm.write_register.i64(metadata !1, i64 0)
21 call void @llvm.write_register.i64(metadata !1, i64 -1)
22 call void @llvm.write_register.i64(metadata !1, i64 %val)
23 call void @llvm.amdgcn.wave.barrier() #1
27 ; CHECK-LABEL: {{^}}test_write_flat_scratch:
28 ; CHECK: s_mov_b64 flat_scratch, 0
29 ; CHECK: s_mov_b64 flat_scratch, -1
30 ; CHECK: s_mov_b64 flat_scratch, s{{\[[0-9]+:[0-9]+\]}}
31 define amdgpu_kernel void @test_write_flat_scratch(i64 %val) #0 {
32 call void @llvm.write_register.i64(metadata !2, i64 0)
33 call void @llvm.write_register.i64(metadata !2, i64 -1)
34 call void @llvm.write_register.i64(metadata !2, i64 %val)
35 call void @llvm.amdgcn.wave.barrier() #1
39 ; CHECK-LABEL: {{^}}test_write_flat_scratch_lo:
40 ; CHECK: s_mov_b32 flat_scratch_lo, 0
41 ; CHECK: s_mov_b32 flat_scratch_lo, s{{[0-9]+}}
42 define amdgpu_kernel void @test_write_flat_scratch_lo(i32 %val) #0 {
43 call void @llvm.write_register.i32(metadata !3, i32 0)
44 call void @llvm.write_register.i32(metadata !3, i32 %val)
45 call void @llvm.amdgcn.wave.barrier() #1
49 ; CHECK-LABEL: {{^}}test_write_flat_scratch_hi:
50 ; CHECK: s_mov_b32 flat_scratch_hi, 0
51 ; CHECK: s_mov_b32 flat_scratch_hi, s{{[0-9]+}}
52 define amdgpu_kernel void @test_write_flat_scratch_hi(i32 %val) #0 {
53 call void @llvm.write_register.i32(metadata !4, i32 0)
54 call void @llvm.write_register.i32(metadata !4, i32 %val)
55 call void @llvm.amdgcn.wave.barrier() #1
59 ; CHECK-LABEL: {{^}}test_write_exec_lo:
60 ; CHECK: s_mov_b32 exec_lo, 0
61 ; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}}
62 define amdgpu_kernel void @test_write_exec_lo(i32 %val) #0 {
63 call void @llvm.write_register.i32(metadata !5, i32 0)
64 call void @llvm.write_register.i32(metadata !5, i32 %val)
65 call void @llvm.amdgcn.wave.barrier() #1
69 ; CHECK-LABEL: {{^}}test_write_exec_hi:
70 ; CHECK: s_mov_b32 exec_hi, 0
71 ; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
72 define amdgpu_kernel void @test_write_exec_hi(i32 %val) #0 {
73 call void @llvm.write_register.i32(metadata !6, i32 0)
74 call void @llvm.write_register.i32(metadata !6, i32 %val)
75 call void @llvm.amdgcn.wave.barrier() #1
79 declare void @llvm.amdgcn.wave.barrier() #1
81 attributes #0 = { nounwind }
82 attributes #1 = { convergent nounwind }
86 !2 = !{!"flat_scratch"}
87 !3 = !{!"flat_scratch_lo"}
88 !4 = !{!"flat_scratch_hi"}