1 ; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX600 %s
2 ; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX700 %s
3 ; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX801 %s
4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX900 %s
5 ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-DL --check-prefix=GFX906 %s
7 ; GCN-LABEL: {{^}}scalar_xnor_i32_one_use
9 define amdgpu_kernel void @scalar_xnor_i32_one_use(
10 i32 addrspace(1)* %r0, i32 %a, i32 %b) {
13 %r0.val = xor i32 %xor, -1
14 store i32 %r0.val, i32 addrspace(1)* %r0
18 ; GCN-LABEL: {{^}}scalar_xnor_i32_mul_use
23 define amdgpu_kernel void @scalar_xnor_i32_mul_use(
24 i32 addrspace(1)* %r0, i32 addrspace(1)* %r1, i32 %a, i32 %b) {
27 %r0.val = xor i32 %xor, -1
28 %r1.val = add i32 %xor, %a
29 store i32 %r0.val, i32 addrspace(1)* %r0
30 store i32 %r1.val, i32 addrspace(1)* %r1
34 ; GCN-LABEL: {{^}}scalar_xnor_i64_one_use
36 define amdgpu_kernel void @scalar_xnor_i64_one_use(
37 i64 addrspace(1)* %r0, i64 %a, i64 %b) {
40 %r0.val = xor i64 %xor, -1
41 store i64 %r0.val, i64 addrspace(1)* %r0
45 ; GCN-LABEL: {{^}}scalar_xnor_i64_mul_use
51 define amdgpu_kernel void @scalar_xnor_i64_mul_use(
52 i64 addrspace(1)* %r0, i64 addrspace(1)* %r1, i64 %a, i64 %b) {
55 %r0.val = xor i64 %xor, -1
56 %r1.val = add i64 %xor, %a
57 store i64 %r0.val, i64 addrspace(1)* %r0
58 store i64 %r1.val, i64 addrspace(1)* %r1
62 ; GCN-LABEL: {{^}}vector_xnor_i32_one_use
67 define i32 @vector_xnor_i32_one_use(i32 %a, i32 %b) {
74 ; GCN-LABEL: {{^}}vector_xnor_i64_one_use
82 define i64 @vector_xnor_i64_one_use(i64 %a, i64 %b) {
89 ; GCN-LABEL: {{^}}xnor_s_v_i32_one_use
93 define amdgpu_kernel void @xnor_s_v_i32_one_use(i32 addrspace(1)* %out, i32 %s) {
94 %v = call i32 @llvm.amdgcn.workitem.id.x() #1
97 store i32 %d, i32 addrspace(1)* %out
101 ; GCN-LABEL: {{^}}xnor_v_s_i32_one_use
102 ; GCN-NOT: s_xnor_b32
105 define amdgpu_kernel void @xnor_v_s_i32_one_use(i32 addrspace(1)* %out, i32 %s) {
106 %v = call i32 @llvm.amdgcn.workitem.id.x() #1
107 %xor = xor i32 %v, %s
108 %d = xor i32 %xor, -1
109 store i32 %d, i32 addrspace(1)* %out
113 ; GCN-LABEL: {{^}}xnor_i64_s_v_one_use
114 ; GCN-NOT: s_xnor_b64
120 define amdgpu_kernel void @xnor_i64_s_v_one_use(
121 i64 addrspace(1)* %r0, i64 %a) {
123 %b32 = call i32 @llvm.amdgcn.workitem.id.x() #1
124 %b64 = zext i32 %b32 to i64
125 %b = shl i64 %b64, 29
126 %xor = xor i64 %a, %b
127 %r0.val = xor i64 %xor, -1
128 store i64 %r0.val, i64 addrspace(1)* %r0
132 ; GCN-LABEL: {{^}}xnor_i64_v_s_one_use
133 ; GCN-NOT: s_xnor_b64
139 define amdgpu_kernel void @xnor_i64_v_s_one_use(
140 i64 addrspace(1)* %r0, i64 %a) {
142 %b32 = call i32 @llvm.amdgcn.workitem.id.x() #1
143 %b64 = zext i32 %b32 to i64
144 %b = shl i64 %b64, 29
145 %xor = xor i64 %b, %a
146 %r0.val = xor i64 %xor, -1
147 store i64 %r0.val, i64 addrspace(1)* %r0
151 ; GCN-LABEL: {{^}}vector_xor_na_b_i32_one_use
152 ; GCN-NOT: s_xnor_b32
156 define i32 @vector_xor_na_b_i32_one_use(i32 %a, i32 %b) {
163 ; GCN-LABEL: {{^}}vector_xor_a_nb_i32_one_use
164 ; GCN-NOT: s_xnor_b32
168 define i32 @vector_xor_a_nb_i32_one_use(i32 %a, i32 %b) {
175 ; GCN-LABEL: {{^}}scalar_xor_a_nb_i64_one_use
177 define amdgpu_kernel void @scalar_xor_a_nb_i64_one_use(
178 i64 addrspace(1)* %r0, i64 %a, i64 %b) {
181 %r0.val = xor i64 %a, %nb
182 store i64 %r0.val, i64 addrspace(1)* %r0
186 ; GCN-LABEL: {{^}}scalar_xor_na_b_i64_one_use
188 define amdgpu_kernel void @scalar_xor_na_b_i64_one_use(
189 i64 addrspace(1)* %r0, i64 %a, i64 %b) {
192 %r0.val = xor i64 %na, %b
193 store i64 %r0.val, i64 addrspace(1)* %r0
197 ; Function Attrs: nounwind readnone
198 declare i32 @llvm.amdgcn.workitem.id.x() #0