1 ; RUN: llc -march=hexagon < %s | FileCheck %s
3 @d = external global <16 x i32>
6 ; CHECK: v{{[0-9]+}}.uw = vcl0(v{{[0-9]+}}.uw)
7 define void @test18(<16 x i32> %a) #0 {
9 %0 = tail call <16 x i32> @llvm.hexagon.V6.vcl0w(<16 x i32> %a)
10 store <16 x i32> %0, <16 x i32>* @d, align 64
14 ; CHECK-LABEL: test19:
15 ; CHECK: v{{[0-9]+}}.h = vpopcount(v{{[0-9]+}}.h)
16 define void @test19(<16 x i32> %a) #0 {
18 %0 = tail call <16 x i32> @llvm.hexagon.V6.vpopcounth(<16 x i32> %a)
19 store <16 x i32> %0, <16 x i32>* @d, align 64
23 ; CHECK-LABEL: test20:
24 ; CHECK: v{{[0-9]+}}.uh = vcl0(v{{[0-9]+}}.uh)
25 define void @test20(<16 x i32> %a) #0 {
27 %0 = tail call <16 x i32> @llvm.hexagon.V6.vcl0h(<16 x i32> %a)
28 store <16 x i32> %0, <16 x i32>* @d, align 64
32 ; CHECK-LABEL: test21:
33 ; CHECK: v{{[0-9]+}}.w = vnormamt(v{{[0-9]+}}.w)
34 define void @test21(<16 x i32> %a) #0 {
36 %0 = tail call <16 x i32> @llvm.hexagon.V6.vnormamtw(<16 x i32> %a)
37 store <16 x i32> %0, <16 x i32>* @d, align 64
41 ; CHECK-LABEL: test22:
42 ; CHECK: v{{[0-9]+}}.h = vnormamt(v{{[0-9]+}}.h)
43 define void @test22(<16 x i32> %a) #0 {
45 %0 = tail call <16 x i32> @llvm.hexagon.V6.vnormamth(<16 x i32> %a)
46 store <16 x i32> %0, <16 x i32>* @d, align 64
50 declare <16 x i32> @llvm.hexagon.V6.vcl0w(<16 x i32>) #0
51 declare <16 x i32> @llvm.hexagon.V6.vpopcounth(<16 x i32>) #0
52 declare <16 x i32> @llvm.hexagon.V6.vcl0h(<16 x i32>) #0
53 declare <16 x i32> @llvm.hexagon.V6.vnormamtw(<16 x i32>) #0
54 declare <16 x i32> @llvm.hexagon.V6.vnormamth(<16 x i32>) #0
56 attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }