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[InstCombine] Signed saturation patterns
[llvm-complete.git]
/
test
/
CodeGen
/
Hexagon
/
neg.ll
blob
f430c130049f7a3cf41ea4d6cdf39191d2a6feda
1
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: f0:
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; CHECK: r0 = sub(#0,r0)
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define i32 @f0(i32 %a0) #0 {
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%v0 = sub i32 0, %a0
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ret i32 %v0
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}
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; CHECK-LABEL: f1:
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; CHECK: r1:0 = neg(r1:0)
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define i64 @f1(i64 %a0) #0 {
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%v0 = sub i64 0, %a0
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ret i64 %v0
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" }