1 ; RUN: llc -march=hexagon < %s | FileCheck %s
3 ; Check for a sane output. This testcase used to cause a crash.
6 target triple = "hexagon-unknown--elf"
8 declare void @halide_malloc() local_unnamed_addr #0
10 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
11 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
12 declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1
13 declare <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32>, <32 x i32>) #1
14 declare <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32>, <64 x i32>) #1
15 declare <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32>, <32 x i32>, i32) #1
16 declare <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32>, <32 x i32>, i32) #1
17 declare <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32>, <32 x i32>, <32 x i32>, i32) #1
19 define hidden void @fred(<32 x i32>* %a0, i32 %a1, i1 %cond) #0 {
22 %v2 = shl nsw i32 %v1, 7
23 switch i32 undef, label %b7 [
33 switch i32 undef, label %b9 [
60 b12: ; preds = %b11, %b10, %b9, %b8
63 b13: ; preds = %b14, %b12
67 br i1 undef, label %b15, label %b13
73 br i1 %cond, label %b17, label %b18
79 tail call void @halide_malloc()
83 %v21 = icmp sgt i32 %a1, 0
84 br i1 %v21, label %b20, label %b21
89 b21: ; preds = %b38, %b19
90 %v22 = zext i32 %v2 to i64
91 %v23 = lshr i64 %v22, 31
92 %v24 = shl nuw nsw i64 %v23, 1
94 %v26 = icmp ult i64 %v23, 2147483648
95 %v27 = mul nuw nsw i64 %v25, 3
96 %v28 = add nuw nsw i64 %v27, 0
97 %v29 = and i64 %v28, 133143986176
98 %v30 = icmp eq i64 %v29, 0
99 %v31 = and i1 %v26, %v30
103 %v33 = zext i32 %v2 to i64
104 %v34 = mul nuw nsw i64 %v33, 12
105 %v35 = icmp ult i64 %v34, 2147483648
106 %v36 = and i1 %v35, undef
107 br i1 %v36, label %b38, label %b37
113 tail call void @halide_malloc()
116 b39: ; preds = %b42, %b21
120 br i1 %v31, label %b42, label %b41
126 %v43 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32> undef, <32 x i32> undef, i32 0)
127 %v44 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v43, <32 x i32> undef, <32 x i32> undef, i32 1)
128 %v45 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v44, <32 x i32> undef, <32 x i32> undef, i32 2)
129 %v46 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v45, <32 x i32> undef, <32 x i32> undef, i32 3)
130 %v47 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v46, <32 x i32> undef, <32 x i32> undef, i32 4)
131 %v48 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v47, <32 x i32> undef, <32 x i32> undef, i32 5)
132 %v49 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v48)
133 %v50 = tail call <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32> undef, <32 x i32> %v49) #2
134 %v51 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> %v50) #2
135 %v52 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v51, <64 x i32> undef) #2
136 %v53 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v52) #2
137 %v54 = tail call <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32> %v53, <32 x i32> undef, i32 15) #2
138 store <32 x i32> %v54, <32 x i32>* %a0, align 128
142 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
143 attributes #1 = { nounwind readnone }
144 attributes #2 = { nounwind }