1 ; RUN: llc -march=hexagon < %s | FileCheck %s
3 ; Check if S4_subi_asl_ri is being generated correctly.
5 ; CHECK-LABEL: yes_sub_asl
6 ; FIXME: We no longer get subi_asl here.
7 ; XCHECK: [[REG1:(r[0-9]+)]] = sub(#0,asl([[REG1]],#1))
8 ; CHECK: [[REG1:(r[0-9]+)]] = asl([[REG1]],#1)
9 ; CHECK: = sub(#0,[[REG1]])
11 ; CHECK-LABEL: no_sub_asl
12 ; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}},#1)
13 ; CHECK: r{{[0-9]+}} = sub([[REG2]],r{{[0-9]+}})
15 %struct.rtx_def = type { i16, i8 }
17 @this_insn_number = external global i32, align 4
19 ; Function Attrs: nounwind
20 define void @yes_sub_asl(%struct.rtx_def* %reg, %struct.rtx_def* nocapture readonly %setter) #0 {
22 %code = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %reg, i32 0, i32 0
23 %0 = load i16, i16* %code, align 4
24 switch i16 %0, label %return [
30 %code6 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %setter, i32 0, i32 0
31 %1 = load i16, i16* %code6, align 4
32 %cmp8 = icmp eq i16 %1, 56
33 %conv9 = zext i1 %cmp8 to i32
34 %2 = load i32, i32* @this_insn_number, align 4
36 %sub = add nsw i32 %conv9, %3
37 tail call void @reg_is_born(%struct.rtx_def* nonnull %reg, i32 %sub) #2
44 declare void @reg_is_born(%struct.rtx_def*, i32) #1
46 ; Function Attrs: nounwind
47 define void @no_sub_asl(%struct.rtx_def* %reg, %struct.rtx_def* nocapture readonly %setter) #0 {
49 %code = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %reg, i32 0, i32 0
50 %0 = load i16, i16* %code, align 4
51 switch i16 %0, label %return [
57 %1 = load i32, i32* @this_insn_number, align 4
58 %mul = mul nsw i32 %1, 2
59 %code6 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %setter, i32 0, i32 0
60 %2 = load i16, i16* %code6, align 4
61 %cmp8 = icmp eq i16 %2, 56
62 %conv9 = zext i1 %cmp8 to i32
63 %sub = sub nsw i32 %mul, %conv9
64 tail call void @reg_is_born(%struct.rtx_def* nonnull %reg, i32 %sub) #2
71 attributes #0 = { nounwind "target-cpu"="hexagonv5" }
72 attributes #1 = { "target-cpu"="hexagonv5" }
73 attributes #2 = { nounwind }