1 ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
3 ; Test that we generate the correct offsets for loads in the prolog
4 ; after removing dependences on a post-increment instructions of the
7 ; CHECK: memh([[REG0:(r[0-9]+)]]+#0)
8 ; CHECK: memh([[REG0]]+#2)
11 ; Function Attrs: nounwind readnone
12 declare i32 @llvm.hexagon.A2.sath(i32) #1
14 ; Function Attrs: nounwind readnone
15 declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #1
17 ; Function Attrs: nounwind readnone
18 declare i32 @llvm.hexagon.A2.asrh(i32) #1
20 ; Function Attrs: nounwind readnone
21 declare i32 @llvm.hexagon.A2.addsat(i32, i32) #1
23 ; Function Attrs: nounwind readnone
24 declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32) #1
26 define void @f0(i32 %a0) #0 align 2 {
33 b2: ; preds = %b2, %b1
34 %v0 = phi i16* [ undef, %b1 ], [ %v14, %b2 ]
35 %v1 = phi i32 [ 0, %b1 ], [ %v12, %b2 ]
36 %v2 = load i16, i16* %v0, align 2
37 %v3 = sext i16 %v2 to i32
38 %v4 = call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 undef, i32 %v3)
39 %v5 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v4, i32 undef)
40 %v6 = call i32 @llvm.hexagon.A2.addsat(i32 %v5, i32 32768)
41 %v7 = call i32 @llvm.hexagon.A2.asrh(i32 %v6)
42 %v8 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v7, i32 undef)
43 %v9 = call i32 @llvm.hexagon.A2.sath(i32 %v8)
44 %v10 = trunc i32 %v9 to i16
45 store i16 %v10, i16* null, align 2
46 %v11 = trunc i32 %v7 to i16
47 store i16 %v11, i16* %v0, align 2
48 %v12 = add nsw i32 %v1, 1
49 %v13 = icmp slt i32 %v12, %a0
50 %v14 = getelementptr i16, i16* %v0, i32 1
51 br i1 %v13, label %b2, label %b3
56 b4: ; No predecessors!
60 attributes #0 = { nounwind "target-cpu"="hexagonv55" }
61 attributes #1 = { nounwind readnone }