1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 -disable-block-placement=0 -hexagon-bit=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
3 ; Test that we rename registers correctly for multiple stages when there is a
4 ; Phi and depends upon another Phi.
8 ; CHECK: r[[REGA:[0-9]+]] = memub(r{{[0-9]+}}+#1)
9 ; CHECK: r[[REG0:[0-9]+]] = and(r[[REG1:[0-9]+]],#255)
10 ; CHECK-NOT: r[[REG0]] = and(r[[REG1]],#255)
11 ; CHECK: loop0(.LBB0_[[LOOP:.]],
12 ; CHECK: .LBB0_[[LOOP]]:
13 ; CHECK: = add(r{{[0-9]+}},r[[REG0]])
15 ; CHECK: r[[REG0]] = and
18 ; Function Attrs: nounwind
19 define void @test(i8* noalias nocapture %src, i32 %srcWidth, i32 %srcHeight, i32 %srcStride, i8* noalias nocapture %dst, i32 %dstStride) #0 {
21 %sub = add i32 %srcWidth, -1
22 %sub1 = add i32 %srcHeight, -1
23 %add.ptr = getelementptr inbounds i8, i8* %src, i32 %srcStride
24 %add.ptr.sum = mul i32 %srcStride, 2
25 %add.ptr2 = getelementptr inbounds i8, i8* %src, i32 %add.ptr.sum
26 br label %for.body.lr.ph
29 %0 = add i32 %srcHeight, -2
30 %1 = mul i32 %0, %dstStride
31 %2 = mul i32 %0, %srcStride
32 %3 = mul i32 %sub1, %srcStride
36 %scevgep = getelementptr i8, i8* %dst, i32 %1
37 %scevgep220 = getelementptr i8, i8* %src, i32 %2
38 %scevgep221 = getelementptr i8, i8* %src, i32 %3
39 %arrayidx6 = getelementptr inbounds i8, i8* %src, i32 1
40 %add11 = add i32 %srcStride, 1
41 %arrayidx12 = getelementptr inbounds i8, i8* %src, i32 %add11
42 br label %for.body75.preheader
45 %sri = load i8, i8* %arrayidx6, align 1
46 %sri224 = load i8, i8* %src, align 1
47 %sri227 = load i8, i8* %arrayidx12, align 1
48 %sri229 = load i8, i8* %add.ptr, align 1
52 %j.0211 = phi i32 [ %add82, %for.body75 ], [ 1, %for.body75.preheader ]
53 %sr = phi i8 [ %4, %for.body75 ], [ %sri, %for.body75.preheader ]
54 %sr225 = phi i8 [ %sr, %for.body75 ], [ %sri224, %for.body75.preheader ]
55 %sr230 = phi i8 [ %5, %for.body75 ], [ %sri227, %for.body75.preheader ]
56 %sr231 = phi i8 [ %sr230, %for.body75 ], [ %sri229, %for.body75.preheader ]
57 %conv78 = zext i8 %sr225 to i32
58 %conv80 = zext i8 %sr to i32
59 %add81 = add nsw i32 %conv80, %conv78
60 %add82 = add i32 %j.0211, 1
61 %arrayidx83 = getelementptr inbounds i8, i8* %src, i32 %add82
62 %4 = load i8, i8* %arrayidx83, align 1, !tbaa !0
63 %conv84 = zext i8 %4 to i32
64 %add85 = add nsw i32 %add81, %conv84
65 %conv88 = zext i8 %sr231 to i32
66 %add89 = add nsw i32 %add85, %conv88
67 %conv91 = zext i8 %sr230 to i32
68 %add92 = add nsw i32 %add89, %conv91
69 %add.ptr.sum208 = add i32 %add82, %srcStride
70 %arrayidx94 = getelementptr inbounds i8, i8* %src, i32 %add.ptr.sum208
71 %5 = load i8, i8* %arrayidx94, align 1, !tbaa !0
72 %conv95 = zext i8 %5 to i32
73 %add96 = add nsw i32 %add92, %conv95
74 %mul97 = mul nsw i32 %add96, 7282
75 %add98 = add nsw i32 %mul97, 32768
76 %shr99209 = lshr i32 %add98, 16
77 %conv100 = trunc i32 %shr99209 to i8
78 %arrayidx101 = getelementptr inbounds i8, i8* %dst, i32 %j.0211
79 store i8 %conv100, i8* %arrayidx101, align 1, !tbaa !0
80 %exitcond = icmp eq i32 %add82, %sub
81 br i1 %exitcond, label %for.end104.loopexit, label %for.body75
90 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
92 !0 = !{!"omnipotent char", !1}
93 !1 = !{!"Simple C/C++ TBAA"}