1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
5 define void @add_i32() {entry: ret void}
6 define void @add_i8_sext() {entry: ret void}
7 define void @add_i8_zext() {entry: ret void}
8 define void @add_i8_aext() {entry: ret void}
9 define void @add_i16_sext() {entry: ret void}
10 define void @add_i16_zext() {entry: ret void}
11 define void @add_i16_aext() {entry: ret void}
12 define void @add_i64() {entry: ret void}
13 define void @add_i128() {entry: ret void}
14 define void @uadd_with_overflow(i32 %lhs, i32 %rhs, i32* %padd, i1* %pcarry_flag) { ret void }
20 tracksRegLiveness: true
25 ; MIPS32-LABEL: name: add_i32
26 ; MIPS32: liveins: $a0, $a1
27 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
28 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
29 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
30 ; MIPS32: $v0 = COPY [[ADD]](s32)
31 ; MIPS32: RetRA implicit $v0
34 %2:_(s32) = G_ADD %0, %1
42 tracksRegLiveness: true
47 ; MIPS32-LABEL: name: add_i8_sext
48 ; MIPS32: liveins: $a0, $a1
49 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
50 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
51 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
52 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
53 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
54 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
55 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
56 ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
57 ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
58 ; MIPS32: $v0 = COPY [[ASHR]](s32)
59 ; MIPS32: RetRA implicit $v0
61 %0:_(s8) = G_TRUNC %2(s32)
63 %1:_(s8) = G_TRUNC %3(s32)
64 %4:_(s8) = G_ADD %1, %0
65 %5:_(s32) = G_SEXT %4(s8)
73 tracksRegLiveness: true
78 ; MIPS32-LABEL: name: add_i8_zext
79 ; MIPS32: liveins: $a0, $a1
80 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
81 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
82 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
83 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
84 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
85 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
86 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
87 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
88 ; MIPS32: $v0 = COPY [[AND]](s32)
89 ; MIPS32: RetRA implicit $v0
91 %0:_(s8) = G_TRUNC %2(s32)
93 %1:_(s8) = G_TRUNC %3(s32)
94 %4:_(s8) = G_ADD %1, %0
95 %5:_(s32) = G_ZEXT %4(s8)
103 tracksRegLiveness: true
108 ; MIPS32-LABEL: name: add_i8_aext
109 ; MIPS32: liveins: $a0, $a1
110 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
111 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
112 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
113 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
114 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
115 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
116 ; MIPS32: $v0 = COPY [[COPY4]](s32)
117 ; MIPS32: RetRA implicit $v0
119 %0:_(s8) = G_TRUNC %2(s32)
121 %1:_(s8) = G_TRUNC %3(s32)
122 %4:_(s8) = G_ADD %1, %0
123 %5:_(s32) = G_ANYEXT %4(s8)
131 tracksRegLiveness: true
136 ; MIPS32-LABEL: name: add_i16_sext
137 ; MIPS32: liveins: $a0, $a1
138 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
139 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
140 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
141 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
142 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
143 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
144 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
145 ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
146 ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
147 ; MIPS32: $v0 = COPY [[ASHR]](s32)
148 ; MIPS32: RetRA implicit $v0
150 %0:_(s16) = G_TRUNC %2(s32)
152 %1:_(s16) = G_TRUNC %3(s32)
153 %4:_(s16) = G_ADD %1, %0
154 %5:_(s32) = G_SEXT %4(s16)
162 tracksRegLiveness: true
167 ; MIPS32-LABEL: name: add_i16_zext
168 ; MIPS32: liveins: $a0, $a1
169 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
170 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
171 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
172 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
173 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
174 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
175 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
176 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
177 ; MIPS32: $v0 = COPY [[AND]](s32)
178 ; MIPS32: RetRA implicit $v0
180 %0:_(s16) = G_TRUNC %2(s32)
182 %1:_(s16) = G_TRUNC %3(s32)
183 %4:_(s16) = G_ADD %1, %0
184 %5:_(s32) = G_ZEXT %4(s16)
192 tracksRegLiveness: true
197 ; MIPS32-LABEL: name: add_i16_aext
198 ; MIPS32: liveins: $a0, $a1
199 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
200 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
201 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
202 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
203 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
204 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
205 ; MIPS32: $v0 = COPY [[COPY4]](s32)
206 ; MIPS32: RetRA implicit $v0
208 %0:_(s16) = G_TRUNC %2(s32)
210 %1:_(s16) = G_TRUNC %3(s32)
211 %4:_(s16) = G_ADD %1, %0
212 %5:_(s32) = G_ANYEXT %4(s16)
220 tracksRegLiveness: true
223 liveins: $a0, $a1, $a2, $a3
225 ; MIPS32-LABEL: name: add_i64
226 ; MIPS32: liveins: $a0, $a1, $a2, $a3
227 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
228 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
229 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
230 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
231 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY1]]
232 ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
233 ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
234 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
235 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
236 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
237 ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
238 ; MIPS32: $v0 = COPY [[ADD2]](s32)
239 ; MIPS32: $v1 = COPY [[ADD]](s32)
240 ; MIPS32: RetRA implicit $v0, implicit $v1
243 %0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32)
246 %1:_(s64) = G_MERGE_VALUES %5(s32), %4(s32)
247 %6:_(s64) = G_ADD %1, %0
248 %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
251 RetRA implicit $v0, implicit $v1
257 tracksRegLiveness: true
259 - { id: 0, offset: 28, size: 4, alignment: 4, stack-id: default, isImmutable: true }
260 - { id: 1, offset: 24, size: 4, alignment: 8, stack-id: default, isImmutable: true }
261 - { id: 2, offset: 20, size: 4, alignment: 4, stack-id: default, isImmutable: true }
262 - { id: 3, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
265 liveins: $a0, $a1, $a2, $a3
267 ; MIPS32-LABEL: name: add_i128
268 ; MIPS32: liveins: $a0, $a1, $a2, $a3
269 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
270 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
271 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
272 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
273 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
274 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0)
275 ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
276 ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1)
277 ; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
278 ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.2)
279 ; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
280 ; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 4 from %fixed-stack.3)
281 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]]
282 ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY]]
283 ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]]
284 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
285 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
286 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
287 ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
288 ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD2]](s32), [[LOAD1]]
289 ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
290 ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
291 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
292 ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND1]]
293 ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[LOAD2]]
294 ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
295 ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
296 ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
297 ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND2]]
298 ; MIPS32: $v0 = COPY [[ADD]](s32)
299 ; MIPS32: $v1 = COPY [[ADD2]](s32)
300 ; MIPS32: $a0 = COPY [[ADD4]](s32)
301 ; MIPS32: $a1 = COPY [[ADD6]](s32)
302 ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
307 %0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
308 %10:_(p0) = G_FRAME_INDEX %fixed-stack.3
309 %6:_(s32) = G_LOAD %10(p0) :: (load 4 from %fixed-stack.3, align 4)
310 %11:_(p0) = G_FRAME_INDEX %fixed-stack.2
311 %7:_(s32) = G_LOAD %11(p0) :: (load 4 from %fixed-stack.2, align 4)
312 %12:_(p0) = G_FRAME_INDEX %fixed-stack.1
313 %8:_(s32) = G_LOAD %12(p0) :: (load 4 from %fixed-stack.1, align 4)
314 %13:_(p0) = G_FRAME_INDEX %fixed-stack.0
315 %9:_(s32) = G_LOAD %13(p0) :: (load 4 from %fixed-stack.0, align 4)
316 %1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
317 %14:_(s128) = G_ADD %1, %0
318 %15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
323 RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
327 name: uadd_with_overflow
329 tracksRegLiveness: true
332 liveins: $a0, $a1, $a2, $a3
334 ; MIPS32-LABEL: name: uadd_with_overflow
335 ; MIPS32: liveins: $a0, $a1, $a2, $a3
336 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
337 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
338 ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
339 ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
340 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
341 ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
342 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
343 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
344 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
345 ; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into %ir.pcarry_flag)
346 ; MIPS32: G_STORE [[ADD]](s32), [[COPY2]](p0) :: (store 4 into %ir.padd)
352 %4:_(s32), %5:_(s1) = G_UADDO %0, %1
353 G_STORE %5(s1), %3(p0) :: (store 1 into %ir.pcarry_flag)
354 G_STORE %4(s32), %2(p0) :: (store 4 into %ir.padd)