| blob | 08e6f70bbe6d9529c7797a0fa04fd999c326c932 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define i64 @test2elt(<2 x i64> %a) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: xxswapd vs0, v2
16 ; CHECK-P8-NEXT: xxlor vs1, v2, v2
17 ; CHECK-P8-NEXT: xscvuxdsp f1, f1
18 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
19 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
20 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
21 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
22 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
23 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
24 ; CHECK-P8-NEXT: xxswapd vs0, v2
25 ; CHECK-P8-NEXT: mfvsrd r3, f0
26 ; CHECK-P8-NEXT: blr
27 ;
28 ; CHECK-P9-LABEL: test2elt:
29 ; CHECK-P9: # %bb.0: # %entry
30 ; CHECK-P9-NEXT: xxswapd vs0, v2
31 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
32 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
33 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
34 ; CHECK-P9-NEXT: xxlor vs0, v2, v2
35 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
36 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
37 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
38 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
39 ; CHECK-P9-NEXT: mfvsrld r3, v2
40 ; CHECK-P9-NEXT: blr
41 ;
42 ; CHECK-BE-LABEL: test2elt:
43 ; CHECK-BE: # %bb.0: # %entry
44 ; CHECK-BE-NEXT: xxswapd vs0, v2
45 ; CHECK-BE-NEXT: xxlor vs1, v2, v2
46 ; CHECK-BE-NEXT: xscvuxdsp f1, f1
47 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
48 ; CHECK-BE-NEXT: xscvdpspn v2, f1
49 ; CHECK-BE-NEXT: xscvdpspn v3, f0
50 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
51 ; CHECK-BE-NEXT: mfvsrd r3, v2
52 ; CHECK-BE-NEXT: blr
53 entry:
54 %0 = uitofp <2 x i64> %a to <2 x float>
55 %1 = bitcast <2 x float> %0 to i64
56 ret i64 %1
57 }
59 define <4 x float> @test4elt(<4 x i64>* nocapture readonly) local_unnamed_addr #1 {
60 ; CHECK-P8-LABEL: test4elt:
61 ; CHECK-P8: # %bb.0: # %entry
62 ; CHECK-P8-NEXT: li r4, 16
63 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
64 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
65 ; CHECK-P8-NEXT: xxswapd v3, vs1
66 ; CHECK-P8-NEXT: xxswapd v2, vs0
67 ; CHECK-P8-NEXT: xvcvuxdsp vs1, v3
68 ; CHECK-P8-NEXT: xvcvuxdsp vs0, v2
69 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
70 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3
71 ; CHECK-P8-NEXT: vpkudum v2, v2, v3
72 ; CHECK-P8-NEXT: blr
73 ;
74 ; CHECK-P9-LABEL: test4elt:
75 ; CHECK-P9: # %bb.0: # %entry
76 ; CHECK-P9-NEXT: lxv v3, 0(r3)
77 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
78 ; CHECK-P9-NEXT: lxv v2, 16(r3)
79 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
80 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v2
81 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
82 ; CHECK-P9-NEXT: vpkudum v2, v2, v3
83 ; CHECK-P9-NEXT: blr
84 ;
85 ; CHECK-BE-LABEL: test4elt:
86 ; CHECK-BE: # %bb.0: # %entry
87 ; CHECK-BE-NEXT: lxv v3, 16(r3)
88 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
89 ; CHECK-BE-NEXT: lxv v2, 0(r3)
90 ; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
91 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v2
92 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
93 ; CHECK-BE-NEXT: vpkudum v2, v2, v3
94 ; CHECK-BE-NEXT: blr
95 entry:
96 %a = load <4 x i64>, <4 x i64>* %0, align 32
97 %1 = uitofp <4 x i64> %a to <4 x float>
98 ret <4 x float> %1
99 }
101 define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #2 {
102 ; CHECK-P8-LABEL: test8elt:
103 ; CHECK-P8: # %bb.0: # %entry
104 ; CHECK-P8-NEXT: li r5, 32
105 ; CHECK-P8-NEXT: li r6, 48
106 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
107 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
108 ; CHECK-P8-NEXT: li r5, 16
109 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
110 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r5
111 ; CHECK-P8-NEXT: xxswapd v5, vs3
112 ; CHECK-P8-NEXT: xxswapd v2, vs0
113 ; CHECK-P8-NEXT: xxswapd v3, vs1
114 ; CHECK-P8-NEXT: xxswapd v4, vs2
115 ; CHECK-P8-NEXT: xvcvuxdsp vs3, v5
116 ; CHECK-P8-NEXT: xvcvuxdsp vs0, v2
117 ; CHECK-P8-NEXT: xvcvuxdsp vs1, v3
118 ; CHECK-P8-NEXT: xvcvuxdsp vs2, v4
119 ; CHECK-P8-NEXT: xxsldwi v5, vs3, vs3, 3
120 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3
121 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
122 ; CHECK-P8-NEXT: xxsldwi v4, vs2, vs2, 3
123 ; CHECK-P8-NEXT: vpkudum v2, v3, v2
124 ; CHECK-P8-NEXT: vpkudum v3, v4, v5
125 ; CHECK-P8-NEXT: stvx v2, r3, r5
126 ; CHECK-P8-NEXT: stvx v3, 0, r3
127 ; CHECK-P8-NEXT: blr
128 ;
129 ; CHECK-P9-LABEL: test8elt:
130 ; CHECK-P9: # %bb.0: # %entry
131 ; CHECK-P9-NEXT: lxv v5, 0(r4)
132 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v5
133 ; CHECK-P9-NEXT: lxv v4, 16(r4)
134 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
135 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v4
136 ; CHECK-P9-NEXT: lxv v3, 32(r4)
137 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
138 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
139 ; CHECK-P9-NEXT: lxv v2, 48(r4)
140 ; CHECK-P9-NEXT: vpkudum v3, v4, v5
141 ; CHECK-P9-NEXT: stxv v3, 0(r3)
142 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
143 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v2
144 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
145 ; CHECK-P9-NEXT: vpkudum v2, v2, v4
146 ; CHECK-P9-NEXT: stxv v2, 16(r3)
147 ; CHECK-P9-NEXT: blr
148 ;
149 ; CHECK-BE-LABEL: test8elt:
150 ; CHECK-BE: # %bb.0: # %entry
151 ; CHECK-BE-NEXT: lxv v5, 16(r4)
152 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v5
153 ; CHECK-BE-NEXT: lxv v4, 0(r4)
154 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
155 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v4
156 ; CHECK-BE-NEXT: lxv v3, 48(r4)
157 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
158 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
159 ; CHECK-BE-NEXT: lxv v2, 32(r4)
160 ; CHECK-BE-NEXT: vpkudum v3, v4, v5
161 ; CHECK-BE-NEXT: stxv v3, 0(r3)
162 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
163 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v2
164 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
165 ; CHECK-BE-NEXT: vpkudum v2, v2, v4
166 ; CHECK-BE-NEXT: stxv v2, 16(r3)
167 ; CHECK-BE-NEXT: blr
168 entry:
169 %a = load <8 x i64>, <8 x i64>* %0, align 64
170 %1 = uitofp <8 x i64> %a to <8 x float>
171 store <8 x float> %1, <8 x float>* %agg.result, align 32
172 ret void
173 }
175 define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i64>* nocapture readonly) local_unnamed_addr #2 {
176 ; CHECK-P8-LABEL: test16elt:
177 ; CHECK-P8: # %bb.0: # %entry
178 ; CHECK-P8-NEXT: li r5, 32
179 ; CHECK-P8-NEXT: li r6, 48
180 ; CHECK-P8-NEXT: li r7, 64
181 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r4
182 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
183 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
184 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
185 ; CHECK-P8-NEXT: li r7, 80
186 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r7
187 ; CHECK-P8-NEXT: li r7, 96
188 ; CHECK-P8-NEXT: xxswapd v2, vs0
189 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r7
190 ; CHECK-P8-NEXT: li r7, 112
191 ; CHECK-P8-NEXT: xxswapd v3, vs1
192 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r7
193 ; CHECK-P8-NEXT: li r7, 16
194 ; CHECK-P8-NEXT: xxswapd v4, vs2
195 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
196 ; CHECK-P8-NEXT: xxswapd v5, vs3
197 ; CHECK-P8-NEXT: xvcvuxdsp vs3, v2
198 ; CHECK-P8-NEXT: xxswapd v2, vs0
199 ; CHECK-P8-NEXT: xvcvuxdsp vs0, v3
200 ; CHECK-P8-NEXT: xxswapd v3, vs1
201 ; CHECK-P8-NEXT: xvcvuxdsp vs1, v4
202 ; CHECK-P8-NEXT: xxswapd v4, vs2
203 ; CHECK-P8-NEXT: xvcvuxdsp vs2, v5
204 ; CHECK-P8-NEXT: xxswapd v5, vs4
205 ; CHECK-P8-NEXT: xvcvuxdsp vs4, v2
206 ; CHECK-P8-NEXT: xvcvuxdsp vs5, v3
207 ; CHECK-P8-NEXT: xvcvuxdsp vs6, v4
208 ; CHECK-P8-NEXT: xxsldwi v2, vs3, vs3, 3
209 ; CHECK-P8-NEXT: xvcvuxdsp vs7, v5
210 ; CHECK-P8-NEXT: xxsldwi v3, vs0, vs0, 3
211 ; CHECK-P8-NEXT: xxsldwi v4, vs1, vs1, 3
212 ; CHECK-P8-NEXT: xxsldwi v5, vs2, vs2, 3
213 ; CHECK-P8-NEXT: xxsldwi v0, vs4, vs4, 3
214 ; CHECK-P8-NEXT: vpkudum v2, v3, v2
215 ; CHECK-P8-NEXT: xxsldwi v1, vs5, vs5, 3
216 ; CHECK-P8-NEXT: xxsldwi v6, vs6, vs6, 3
217 ; CHECK-P8-NEXT: vpkudum v3, v5, v4
218 ; CHECK-P8-NEXT: xxsldwi v7, vs7, vs7, 3
219 ; CHECK-P8-NEXT: vpkudum v4, v1, v0
220 ; CHECK-P8-NEXT: vpkudum v5, v6, v7
221 ; CHECK-P8-NEXT: stvx v2, r3, r7
222 ; CHECK-P8-NEXT: stvx v3, r3, r5
223 ; CHECK-P8-NEXT: stvx v4, r3, r6
224 ; CHECK-P8-NEXT: stvx v5, 0, r3
225 ; CHECK-P8-NEXT: blr
226 ;
227 ; CHECK-P9-LABEL: test16elt:
228 ; CHECK-P9: # %bb.0: # %entry
229 ; CHECK-P9-NEXT: lxv v7, 0(r4)
230 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v7
231 ; CHECK-P9-NEXT: lxv v6, 16(r4)
232 ; CHECK-P9-NEXT: xxsldwi v7, vs0, vs0, 3
233 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v6
234 ; CHECK-P9-NEXT: lxv v1, 32(r4)
235 ; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
236 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v1
237 ; CHECK-P9-NEXT: lxv v0, 48(r4)
238 ; CHECK-P9-NEXT: vpkudum v1, v6, v7
239 ; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
240 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v0
241 ; CHECK-P9-NEXT: lxv v5, 64(r4)
242 ; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3
243 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v5
244 ; CHECK-P9-NEXT: lxv v4, 80(r4)
245 ; CHECK-P9-NEXT: vpkudum v0, v0, v6
246 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
247 ; CHECK-P9-NEXT: lxv v3, 96(r4)
248 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v4
249 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
250 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
251 ; CHECK-P9-NEXT: lxv v2, 112(r4)
252 ; CHECK-P9-NEXT: stxv v0, 16(r3)
253 ; CHECK-P9-NEXT: stxv v1, 0(r3)
254 ; CHECK-P9-NEXT: vpkudum v4, v4, v5
255 ; CHECK-P9-NEXT: stxv v4, 32(r3)
256 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
257 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v2
258 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
259 ; CHECK-P9-NEXT: vpkudum v2, v2, v3
260 ; CHECK-P9-NEXT: stxv v2, 48(r3)
261 ; CHECK-P9-NEXT: blr
262 ;
263 ; CHECK-BE-LABEL: test16elt:
264 ; CHECK-BE: # %bb.0: # %entry
265 ; CHECK-BE-NEXT: lxv v7, 16(r4)
266 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v7
267 ; CHECK-BE-NEXT: lxv v6, 0(r4)
268 ; CHECK-BE-NEXT: xxsldwi v7, vs0, vs0, 3
269 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v6
270 ; CHECK-BE-NEXT: lxv v1, 48(r4)
271 ; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
272 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v1
273 ; CHECK-BE-NEXT: lxv v0, 32(r4)
274 ; CHECK-BE-NEXT: vpkudum v1, v6, v7
275 ; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
276 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v0
277 ; CHECK-BE-NEXT: lxv v5, 80(r4)
278 ; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3
279 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v5
280 ; CHECK-BE-NEXT: lxv v4, 64(r4)
281 ; CHECK-BE-NEXT: vpkudum v0, v0, v6
282 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
283 ; CHECK-BE-NEXT: lxv v3, 112(r4)
284 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v4
285 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
286 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
287 ; CHECK-BE-NEXT: lxv v2, 96(r4)
288 ; CHECK-BE-NEXT: stxv v0, 16(r3)
289 ; CHECK-BE-NEXT: stxv v1, 0(r3)
290 ; CHECK-BE-NEXT: vpkudum v4, v4, v5
291 ; CHECK-BE-NEXT: stxv v4, 32(r3)
292 ; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
293 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v2
294 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
295 ; CHECK-BE-NEXT: vpkudum v2, v2, v3
296 ; CHECK-BE-NEXT: stxv v2, 48(r3)
297 ; CHECK-BE-NEXT: blr
298 entry:
299 %a = load <16 x i64>, <16 x i64>* %0, align 128
300 %1 = uitofp <16 x i64> %a to <16 x float>
301 store <16 x float> %1, <16 x float>* %agg.result, align 64
302 ret void
303 }
305 define i64 @test2elt_signed(<2 x i64> %a) local_unnamed_addr #0 {
306 ; CHECK-P8-LABEL: test2elt_signed:
307 ; CHECK-P8: # %bb.0: # %entry
308 ; CHECK-P8-NEXT: xxswapd vs0, v2
309 ; CHECK-P8-NEXT: xxlor vs1, v2, v2
310 ; CHECK-P8-NEXT: xscvsxdsp f1, f1
311 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
312 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
313 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
314 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
315 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
316 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
317 ; CHECK-P8-NEXT: xxswapd vs0, v2
318 ; CHECK-P8-NEXT: mfvsrd r3, f0
319 ; CHECK-P8-NEXT: blr
320 ;
321 ; CHECK-P9-LABEL: test2elt_signed:
322 ; CHECK-P9: # %bb.0: # %entry
323 ; CHECK-P9-NEXT: xxswapd vs0, v2
324 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
325 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
326 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
327 ; CHECK-P9-NEXT: xxlor vs0, v2, v2
328 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
329 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
330 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
331 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
332 ; CHECK-P9-NEXT: mfvsrld r3, v2
333 ; CHECK-P9-NEXT: blr
334 ;
335 ; CHECK-BE-LABEL: test2elt_signed:
336 ; CHECK-BE: # %bb.0: # %entry
337 ; CHECK-BE-NEXT: xxswapd vs0, v2
338 ; CHECK-BE-NEXT: xxlor vs1, v2, v2
339 ; CHECK-BE-NEXT: xscvsxdsp f1, f1
340 ; CHECK-BE-NEXT: xscvsxdsp f0, f0
341 ; CHECK-BE-NEXT: xscvdpspn v2, f1
342 ; CHECK-BE-NEXT: xscvdpspn v3, f0
343 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
344 ; CHECK-BE-NEXT: mfvsrd r3, v2
345 ; CHECK-BE-NEXT: blr
346 entry:
347 %0 = sitofp <2 x i64> %a to <2 x float>
348 %1 = bitcast <2 x float> %0 to i64
349 ret i64 %1
350 }
352 define <4 x float> @test4elt_signed(<4 x i64>* nocapture readonly) local_unnamed_addr #1 {
353 ; CHECK-P8-LABEL: test4elt_signed:
354 ; CHECK-P8: # %bb.0: # %entry
355 ; CHECK-P8-NEXT: li r4, 16
356 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
357 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
358 ; CHECK-P8-NEXT: xxswapd v3, vs1
359 ; CHECK-P8-NEXT: xxswapd v2, vs0
360 ; CHECK-P8-NEXT: xvcvsxdsp vs1, v3
361 ; CHECK-P8-NEXT: xvcvsxdsp vs0, v2
362 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
363 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3
364 ; CHECK-P8-NEXT: vpkudum v2, v2, v3
365 ; CHECK-P8-NEXT: blr
366 ;
367 ; CHECK-P9-LABEL: test4elt_signed:
368 ; CHECK-P9: # %bb.0: # %entry
369 ; CHECK-P9-NEXT: lxv v3, 0(r3)
370 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
371 ; CHECK-P9-NEXT: lxv v2, 16(r3)
372 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
373 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v2
374 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
375 ; CHECK-P9-NEXT: vpkudum v2, v2, v3
376 ; CHECK-P9-NEXT: blr
377 ;
378 ; CHECK-BE-LABEL: test4elt_signed:
379 ; CHECK-BE: # %bb.0: # %entry
380 ; CHECK-BE-NEXT: lxv v3, 16(r3)
381 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
382 ; CHECK-BE-NEXT: lxv v2, 0(r3)
383 ; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
384 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v2
385 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
386 ; CHECK-BE-NEXT: vpkudum v2, v2, v3
387 ; CHECK-BE-NEXT: blr
388 entry:
389 %a = load <4 x i64>, <4 x i64>* %0, align 32
390 %1 = sitofp <4 x i64> %a to <4 x float>
391 ret <4 x float> %1
392 }
394 define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #2 {
395 ; CHECK-P8-LABEL: test8elt_signed:
396 ; CHECK-P8: # %bb.0: # %entry
397 ; CHECK-P8-NEXT: li r5, 32
398 ; CHECK-P8-NEXT: li r6, 48
399 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
400 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
401 ; CHECK-P8-NEXT: li r5, 16
402 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
403 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r5
404 ; CHECK-P8-NEXT: xxswapd v5, vs3
405 ; CHECK-P8-NEXT: xxswapd v2, vs0
406 ; CHECK-P8-NEXT: xxswapd v3, vs1
407 ; CHECK-P8-NEXT: xxswapd v4, vs2
408 ; CHECK-P8-NEXT: xvcvsxdsp vs3, v5
409 ; CHECK-P8-NEXT: xvcvsxdsp vs0, v2
410 ; CHECK-P8-NEXT: xvcvsxdsp vs1, v3
411 ; CHECK-P8-NEXT: xvcvsxdsp vs2, v4
412 ; CHECK-P8-NEXT: xxsldwi v5, vs3, vs3, 3
413 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3
414 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
415 ; CHECK-P8-NEXT: xxsldwi v4, vs2, vs2, 3
416 ; CHECK-P8-NEXT: vpkudum v2, v3, v2
417 ; CHECK-P8-NEXT: vpkudum v3, v4, v5
418 ; CHECK-P8-NEXT: stvx v2, r3, r5
419 ; CHECK-P8-NEXT: stvx v3, 0, r3
420 ; CHECK-P8-NEXT: blr
421 ;
422 ; CHECK-P9-LABEL: test8elt_signed:
423 ; CHECK-P9: # %bb.0: # %entry
424 ; CHECK-P9-NEXT: lxv v5, 0(r4)
425 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v5
426 ; CHECK-P9-NEXT: lxv v4, 16(r4)
427 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
428 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v4
429 ; CHECK-P9-NEXT: lxv v3, 32(r4)
430 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
431 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
432 ; CHECK-P9-NEXT: lxv v2, 48(r4)
433 ; CHECK-P9-NEXT: vpkudum v3, v4, v5
434 ; CHECK-P9-NEXT: stxv v3, 0(r3)
435 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
436 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v2
437 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
438 ; CHECK-P9-NEXT: vpkudum v2, v2, v4
439 ; CHECK-P9-NEXT: stxv v2, 16(r3)
440 ; CHECK-P9-NEXT: blr
441 ;
442 ; CHECK-BE-LABEL: test8elt_signed:
443 ; CHECK-BE: # %bb.0: # %entry
444 ; CHECK-BE-NEXT: lxv v5, 16(r4)
445 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v5
446 ; CHECK-BE-NEXT: lxv v4, 0(r4)
447 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
448 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v4
449 ; CHECK-BE-NEXT: lxv v3, 48(r4)
450 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
451 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
452 ; CHECK-BE-NEXT: lxv v2, 32(r4)
453 ; CHECK-BE-NEXT: vpkudum v3, v4, v5
454 ; CHECK-BE-NEXT: stxv v3, 0(r3)
455 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
456 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v2
457 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
458 ; CHECK-BE-NEXT: vpkudum v2, v2, v4
459 ; CHECK-BE-NEXT: stxv v2, 16(r3)
460 ; CHECK-BE-NEXT: blr
461 entry:
462 %a = load <8 x i64>, <8 x i64>* %0, align 64
463 %1 = sitofp <8 x i64> %a to <8 x float>
464 store <8 x float> %1, <8 x float>* %agg.result, align 32
465 ret void
466 }
468 define void @test16elt_signed(<16 x float>* noalias nocapture sret %agg.result, <16 x i64>* nocapture readonly) local_unnamed_addr #2 {
469 ; CHECK-P8-LABEL: test16elt_signed:
470 ; CHECK-P8: # %bb.0: # %entry
471 ; CHECK-P8-NEXT: li r5, 32
472 ; CHECK-P8-NEXT: li r6, 48
473 ; CHECK-P8-NEXT: li r7, 64
474 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r4
475 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
476 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
477 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
478 ; CHECK-P8-NEXT: li r7, 80
479 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r7
480 ; CHECK-P8-NEXT: li r7, 96
481 ; CHECK-P8-NEXT: xxswapd v2, vs0
482 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r7
483 ; CHECK-P8-NEXT: li r7, 112
484 ; CHECK-P8-NEXT: xxswapd v3, vs1
485 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r7
486 ; CHECK-P8-NEXT: li r7, 16
487 ; CHECK-P8-NEXT: xxswapd v4, vs2
488 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
489 ; CHECK-P8-NEXT: xxswapd v5, vs3
490 ; CHECK-P8-NEXT: xvcvsxdsp vs3, v2
491 ; CHECK-P8-NEXT: xxswapd v2, vs0
492 ; CHECK-P8-NEXT: xvcvsxdsp vs0, v3
493 ; CHECK-P8-NEXT: xxswapd v3, vs1
494 ; CHECK-P8-NEXT: xvcvsxdsp vs1, v4
495 ; CHECK-P8-NEXT: xxswapd v4, vs2
496 ; CHECK-P8-NEXT: xvcvsxdsp vs2, v5
497 ; CHECK-P8-NEXT: xxswapd v5, vs4
498 ; CHECK-P8-NEXT: xvcvsxdsp vs4, v2
499 ; CHECK-P8-NEXT: xvcvsxdsp vs5, v3
500 ; CHECK-P8-NEXT: xvcvsxdsp vs6, v4
501 ; CHECK-P8-NEXT: xxsldwi v2, vs3, vs3, 3
502 ; CHECK-P8-NEXT: xvcvsxdsp vs7, v5
503 ; CHECK-P8-NEXT: xxsldwi v3, vs0, vs0, 3
504 ; CHECK-P8-NEXT: xxsldwi v4, vs1, vs1, 3
505 ; CHECK-P8-NEXT: xxsldwi v5, vs2, vs2, 3
506 ; CHECK-P8-NEXT: xxsldwi v0, vs4, vs4, 3
507 ; CHECK-P8-NEXT: vpkudum v2, v3, v2
508 ; CHECK-P8-NEXT: xxsldwi v1, vs5, vs5, 3
509 ; CHECK-P8-NEXT: xxsldwi v6, vs6, vs6, 3
510 ; CHECK-P8-NEXT: vpkudum v3, v5, v4
511 ; CHECK-P8-NEXT: xxsldwi v7, vs7, vs7, 3
512 ; CHECK-P8-NEXT: vpkudum v4, v1, v0
513 ; CHECK-P8-NEXT: vpkudum v5, v6, v7
514 ; CHECK-P8-NEXT: stvx v2, r3, r7
515 ; CHECK-P8-NEXT: stvx v3, r3, r5
516 ; CHECK-P8-NEXT: stvx v4, r3, r6
517 ; CHECK-P8-NEXT: stvx v5, 0, r3
518 ; CHECK-P8-NEXT: blr
519 ;
520 ; CHECK-P9-LABEL: test16elt_signed:
521 ; CHECK-P9: # %bb.0: # %entry
522 ; CHECK-P9-NEXT: lxv v7, 0(r4)
523 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v7
524 ; CHECK-P9-NEXT: lxv v6, 16(r4)
525 ; CHECK-P9-NEXT: xxsldwi v7, vs0, vs0, 3
526 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v6
527 ; CHECK-P9-NEXT: lxv v1, 32(r4)
528 ; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
529 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v1
530 ; CHECK-P9-NEXT: lxv v0, 48(r4)
531 ; CHECK-P9-NEXT: vpkudum v1, v6, v7
532 ; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
533 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v0
534 ; CHECK-P9-NEXT: lxv v5, 64(r4)
535 ; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3
536 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v5
537 ; CHECK-P9-NEXT: lxv v4, 80(r4)
538 ; CHECK-P9-NEXT: vpkudum v0, v0, v6
539 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
540 ; CHECK-P9-NEXT: lxv v3, 96(r4)
541 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v4
542 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
543 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
544 ; CHECK-P9-NEXT: lxv v2, 112(r4)
545 ; CHECK-P9-NEXT: stxv v0, 16(r3)
546 ; CHECK-P9-NEXT: stxv v1, 0(r3)
547 ; CHECK-P9-NEXT: vpkudum v4, v4, v5
548 ; CHECK-P9-NEXT: stxv v4, 32(r3)
549 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
550 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v2
551 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
552 ; CHECK-P9-NEXT: vpkudum v2, v2, v3
553 ; CHECK-P9-NEXT: stxv v2, 48(r3)
554 ; CHECK-P9-NEXT: blr
555 ;
556 ; CHECK-BE-LABEL: test16elt_signed:
557 ; CHECK-BE: # %bb.0: # %entry
558 ; CHECK-BE-NEXT: lxv v7, 16(r4)
559 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v7
560 ; CHECK-BE-NEXT: lxv v6, 0(r4)
561 ; CHECK-BE-NEXT: xxsldwi v7, vs0, vs0, 3
562 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v6
563 ; CHECK-BE-NEXT: lxv v1, 48(r4)
564 ; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
565 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v1
566 ; CHECK-BE-NEXT: lxv v0, 32(r4)
567 ; CHECK-BE-NEXT: vpkudum v1, v6, v7
568 ; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
569 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v0
570 ; CHECK-BE-NEXT: lxv v5, 80(r4)
571 ; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3
572 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v5
573 ; CHECK-BE-NEXT: lxv v4, 64(r4)
574 ; CHECK-BE-NEXT: vpkudum v0, v0, v6
575 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
576 ; CHECK-BE-NEXT: lxv v3, 112(r4)
577 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v4
578 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
579 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
580 ; CHECK-BE-NEXT: lxv v2, 96(r4)
581 ; CHECK-BE-NEXT: stxv v0, 16(r3)
582 ; CHECK-BE-NEXT: stxv v1, 0(r3)
583 ; CHECK-BE-NEXT: vpkudum v4, v4, v5
584 ; CHECK-BE-NEXT: stxv v4, 32(r3)
585 ; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
586 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v2
587 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
588 ; CHECK-BE-NEXT: vpkudum v2, v2, v3
589 ; CHECK-BE-NEXT: stxv v2, 48(r3)
590 ; CHECK-BE-NEXT: blr
591 entry:
592 %a = load <16 x i64>, <16 x i64>* %0, align 128
593 %1 = sitofp <16 x i64> %a to <16 x float>
594 store <16 x float> %1, <16 x float>* %agg.result, align 64
595 ret void
596 }