1 ; Test vector addition on z14.
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
5 ; Test a v4f32 addition.
6 define <4 x float> @f1(<4 x float> %dummy, <4 x float> %val1,
9 ; CHECK: vfasb %v24, %v26, %v28
11 %ret = fadd <4 x float> %val1, %val2
15 ; Test an f32 addition that uses vector registers.
16 define float @f2(<4 x float> %val1, <4 x float> %val2) {
18 ; CHECK: wfasb %f0, %v24, %v26
20 %scalar1 = extractelement <4 x float> %val1, i32 0
21 %scalar2 = extractelement <4 x float> %val2, i32 0
22 %ret = fadd float %scalar1, %scalar2