1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi, -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-FP
3 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi, -mattr=+mve.fp -fp-contract=fast -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-VMLA
4 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE
6 define arm_aapcs_vfpcc <8 x half> @vfma16_v1(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
7 ; CHECK-MVE-FP-LABEL: vfma16_v1:
8 ; CHECK-MVE-FP: @ %bb.0: @ %entry
9 ; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
10 ; CHECK-MVE-FP-NEXT: vadd.f16 q0, q0, q1
11 ; CHECK-MVE-FP-NEXT: bx lr
13 ; CHECK-MVE-VMLA-LABEL: vfma16_v1:
14 ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
15 ; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2
16 ; CHECK-MVE-VMLA-NEXT: bx lr
18 ; CHECK-MVE-LABEL: vfma16_v1:
19 ; CHECK-MVE: @ %bb.0: @ %entry
20 ; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
21 ; CHECK-MVE-NEXT: vpush {d8, d9, d10}
22 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
23 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
24 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
25 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
26 ; CHECK-MVE-NEXT: vmov.f32 s16, s1
27 ; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
28 ; CHECK-MVE-NEXT: vmov r1, s0
29 ; CHECK-MVE-NEXT: vmla.f16 s16, s5, s9
30 ; CHECK-MVE-NEXT: vmov r0, s13
31 ; CHECK-MVE-NEXT: vmov.16 q3[0], r1
32 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
33 ; CHECK-MVE-NEXT: vmov r0, s16
34 ; CHECK-MVE-NEXT: vmovx.f16 s16, s9
35 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
36 ; CHECK-MVE-NEXT: vmovx.f16 s20, s1
37 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
38 ; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
39 ; CHECK-MVE-NEXT: vmov.f32 s16, s2
40 ; CHECK-MVE-NEXT: vmov r0, s20
41 ; CHECK-MVE-NEXT: vmla.f16 s16, s6, s10
42 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
43 ; CHECK-MVE-NEXT: vmov r0, s16
44 ; CHECK-MVE-NEXT: vmovx.f16 s16, s10
45 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
46 ; CHECK-MVE-NEXT: vmovx.f16 s20, s2
47 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
48 ; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
49 ; CHECK-MVE-NEXT: vmov.f32 s16, s3
50 ; CHECK-MVE-NEXT: vmov r0, s20
51 ; CHECK-MVE-NEXT: vmla.f16 s16, s7, s11
52 ; CHECK-MVE-NEXT: vmovx.f16 s8, s11
53 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
54 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
55 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
56 ; CHECK-MVE-NEXT: vmov r0, s16
57 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
58 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
59 ; CHECK-MVE-NEXT: vmov r0, s0
60 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
61 ; CHECK-MVE-NEXT: vmov q0, q3
62 ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
63 ; CHECK-MVE-NEXT: bx lr
65 %0 = fmul <8 x half> %src2, %src3
66 %1 = fadd <8 x half> %src1, %0
70 define arm_aapcs_vfpcc <8 x half> @vfma16_v2(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
71 ; CHECK-MVE-FP-LABEL: vfma16_v2:
72 ; CHECK-MVE-FP: @ %bb.0: @ %entry
73 ; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
74 ; CHECK-MVE-FP-NEXT: vadd.f16 q0, q1, q0
75 ; CHECK-MVE-FP-NEXT: bx lr
77 ; CHECK-MVE-VMLA-LABEL: vfma16_v2:
78 ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
79 ; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2
80 ; CHECK-MVE-VMLA-NEXT: bx lr
82 ; CHECK-MVE-LABEL: vfma16_v2:
83 ; CHECK-MVE: @ %bb.0: @ %entry
84 ; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
85 ; CHECK-MVE-NEXT: vpush {d8, d9, d10}
86 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
87 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
88 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
89 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
90 ; CHECK-MVE-NEXT: vmov.f32 s16, s1
91 ; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
92 ; CHECK-MVE-NEXT: vmov r1, s0
93 ; CHECK-MVE-NEXT: vmla.f16 s16, s5, s9
94 ; CHECK-MVE-NEXT: vmov r0, s13
95 ; CHECK-MVE-NEXT: vmov.16 q3[0], r1
96 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
97 ; CHECK-MVE-NEXT: vmov r0, s16
98 ; CHECK-MVE-NEXT: vmovx.f16 s16, s9
99 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
100 ; CHECK-MVE-NEXT: vmovx.f16 s20, s1
101 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
102 ; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
103 ; CHECK-MVE-NEXT: vmov.f32 s16, s2
104 ; CHECK-MVE-NEXT: vmov r0, s20
105 ; CHECK-MVE-NEXT: vmla.f16 s16, s6, s10
106 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
107 ; CHECK-MVE-NEXT: vmov r0, s16
108 ; CHECK-MVE-NEXT: vmovx.f16 s16, s10
109 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
110 ; CHECK-MVE-NEXT: vmovx.f16 s20, s2
111 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
112 ; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
113 ; CHECK-MVE-NEXT: vmov.f32 s16, s3
114 ; CHECK-MVE-NEXT: vmov r0, s20
115 ; CHECK-MVE-NEXT: vmla.f16 s16, s7, s11
116 ; CHECK-MVE-NEXT: vmovx.f16 s8, s11
117 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
118 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
119 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
120 ; CHECK-MVE-NEXT: vmov r0, s16
121 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
122 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
123 ; CHECK-MVE-NEXT: vmov r0, s0
124 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
125 ; CHECK-MVE-NEXT: vmov q0, q3
126 ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
127 ; CHECK-MVE-NEXT: bx lr
129 %0 = fmul <8 x half> %src2, %src3
130 %1 = fadd <8 x half> %0, %src1
134 define arm_aapcs_vfpcc <8 x half> @vfms16(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
135 ; CHECK-MVE-FP-LABEL: vfms16:
136 ; CHECK-MVE-FP: @ %bb.0: @ %entry
137 ; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
138 ; CHECK-MVE-FP-NEXT: vsub.f16 q0, q0, q1
139 ; CHECK-MVE-FP-NEXT: bx lr
141 ; CHECK-MVE-VMLA-LABEL: vfms16:
142 ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
143 ; CHECK-MVE-VMLA-NEXT: vfms.f16 q0, q1, q2
144 ; CHECK-MVE-VMLA-NEXT: bx lr
146 ; CHECK-MVE-LABEL: vfms16:
147 ; CHECK-MVE: @ %bb.0: @ %entry
148 ; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
149 ; CHECK-MVE-NEXT: vpush {d8, d9, d10}
150 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
151 ; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8
152 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
153 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
154 ; CHECK-MVE-NEXT: vmov.f32 s16, s1
155 ; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
156 ; CHECK-MVE-NEXT: vmov r1, s0
157 ; CHECK-MVE-NEXT: vmls.f16 s16, s5, s9
158 ; CHECK-MVE-NEXT: vmov r0, s13
159 ; CHECK-MVE-NEXT: vmov.16 q3[0], r1
160 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
161 ; CHECK-MVE-NEXT: vmov r0, s16
162 ; CHECK-MVE-NEXT: vmovx.f16 s16, s9
163 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
164 ; CHECK-MVE-NEXT: vmovx.f16 s20, s1
165 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
166 ; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
167 ; CHECK-MVE-NEXT: vmov.f32 s16, s2
168 ; CHECK-MVE-NEXT: vmov r0, s20
169 ; CHECK-MVE-NEXT: vmls.f16 s16, s6, s10
170 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
171 ; CHECK-MVE-NEXT: vmov r0, s16
172 ; CHECK-MVE-NEXT: vmovx.f16 s16, s10
173 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
174 ; CHECK-MVE-NEXT: vmovx.f16 s20, s2
175 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
176 ; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
177 ; CHECK-MVE-NEXT: vmov.f32 s16, s3
178 ; CHECK-MVE-NEXT: vmov r0, s20
179 ; CHECK-MVE-NEXT: vmls.f16 s16, s7, s11
180 ; CHECK-MVE-NEXT: vmovx.f16 s8, s11
181 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
182 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
183 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
184 ; CHECK-MVE-NEXT: vmov r0, s16
185 ; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8
186 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
187 ; CHECK-MVE-NEXT: vmov r0, s0
188 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
189 ; CHECK-MVE-NEXT: vmov q0, q3
190 ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
191 ; CHECK-MVE-NEXT: bx lr
193 %0 = fmul <8 x half> %src2, %src3
194 %1 = fsub <8 x half> %src1, %0
198 define arm_aapcs_vfpcc <4 x float> @vfma32_v1(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
199 ; CHECK-MVE-FP-LABEL: vfma32_v1:
200 ; CHECK-MVE-FP: @ %bb.0: @ %entry
201 ; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2
202 ; CHECK-MVE-FP-NEXT: vadd.f32 q0, q0, q1
203 ; CHECK-MVE-FP-NEXT: bx lr
205 ; CHECK-MVE-VMLA-LABEL: vfma32_v1:
206 ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
207 ; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, q2
208 ; CHECK-MVE-VMLA-NEXT: bx lr
210 ; CHECK-MVE-LABEL: vfma32_v1:
211 ; CHECK-MVE: @ %bb.0: @ %entry
212 ; CHECK-MVE-NEXT: vmla.f32 s3, s7, s11
213 ; CHECK-MVE-NEXT: vmla.f32 s2, s6, s10
214 ; CHECK-MVE-NEXT: vmla.f32 s1, s5, s9
215 ; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8
216 ; CHECK-MVE-NEXT: bx lr
218 %0 = fmul <4 x float> %src2, %src3
219 %1 = fadd <4 x float> %src1, %0
223 define arm_aapcs_vfpcc <4 x float> @vfma32_v2(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
224 ; CHECK-MVE-FP-LABEL: vfma32_v2:
225 ; CHECK-MVE-FP: @ %bb.0: @ %entry
226 ; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2
227 ; CHECK-MVE-FP-NEXT: vadd.f32 q0, q1, q0
228 ; CHECK-MVE-FP-NEXT: bx lr
230 ; CHECK-MVE-VMLA-LABEL: vfma32_v2:
231 ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
232 ; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, q2
233 ; CHECK-MVE-VMLA-NEXT: bx lr
235 ; CHECK-MVE-LABEL: vfma32_v2:
236 ; CHECK-MVE: @ %bb.0: @ %entry
237 ; CHECK-MVE-NEXT: vmla.f32 s3, s7, s11
238 ; CHECK-MVE-NEXT: vmla.f32 s2, s6, s10
239 ; CHECK-MVE-NEXT: vmla.f32 s1, s5, s9
240 ; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8
241 ; CHECK-MVE-NEXT: bx lr
243 %0 = fmul <4 x float> %src2, %src3
244 %1 = fadd <4 x float> %0, %src1
248 define arm_aapcs_vfpcc <4 x float> @vfms32(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
249 ; CHECK-MVE-FP-LABEL: vfms32:
250 ; CHECK-MVE-FP: @ %bb.0: @ %entry
251 ; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2
252 ; CHECK-MVE-FP-NEXT: vsub.f32 q0, q0, q1
253 ; CHECK-MVE-FP-NEXT: bx lr
255 ; CHECK-MVE-VMLA-LABEL: vfms32:
256 ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
257 ; CHECK-MVE-VMLA-NEXT: vfms.f32 q0, q1, q2
258 ; CHECK-MVE-VMLA-NEXT: bx lr
260 ; CHECK-MVE-LABEL: vfms32:
261 ; CHECK-MVE: @ %bb.0: @ %entry
262 ; CHECK-MVE-NEXT: vmls.f32 s3, s7, s11
263 ; CHECK-MVE-NEXT: vmls.f32 s2, s6, s10
264 ; CHECK-MVE-NEXT: vmls.f32 s1, s5, s9
265 ; CHECK-MVE-NEXT: vmls.f32 s0, s4, s8
266 ; CHECK-MVE-NEXT: bx lr
268 %0 = fmul <4 x float> %src2, %src3
269 %1 = fsub <4 x float> %src1, %0