[InstCombine] Signed saturation patterns
[llvm-complete.git] / test / MC / AArch64 / SVE / bic-diagnostics.s
blob099009bc6a63044de78ab9e1fa17a5a0f0a5ac1f
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 // --------------------------------------------------------------------------//
4 // Immediate not compatible with encode/decode function.
6 bic z5.b, z5.b, #0xfa
7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
8 // CHECK-NEXT: bic z5.b, z5.b, #0xfa
9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11 bic z5.b, z5.b, #0xfff9
12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
13 // CHECK-NEXT: bic z5.b, z5.b, #0xfff9
14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16 bic z5.h, z5.h, #0xfffa
17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
18 // CHECK-NEXT: bic z5.h, z5.h, #0xfffa
19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21 bic z5.h, z5.h, #0xfffffff9
22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
23 // CHECK-NEXT: bic z5.h, z5.h, #0xfffffff9
24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26 bic z5.s, z5.s, #0xfffffffa
27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
28 // CHECK-NEXT: bic z5.s, z5.s, #0xfffffffa
29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
31 bic z5.s, z5.s, #0xffffffffffffff9
32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
33 // CHECK-NEXT: bic z5.s, z5.s, #0xffffffffffffff9
34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
36 bic z15.d, z15.d, #0xfffffffffffffffa
37 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
38 // CHECK-NEXT: bic z15.d, z15.d, #0xfffffffffffffffa
39 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
41 // --------------------------------------------------------------------------//
42 // Source and Destination Registers must match
44 bic z7.d, z8.d, #254
45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
46 // CHECK-NEXT: bic z7.d, z8.d, #254
47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
49 bic z0.d, p0/m, z1.d, z2.d
50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
51 // CHECK-NEXT: bic z0.d, p0/m, z1.d, z2.d
52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
54 // Element size specifiers should match.
55 bic z21.d, z5.d, z26.b
56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
57 // CHECK-NEXT: bic z21.d, z5.d, z26.b
58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
61 // --------------------------------------------------------------------------//
62 // Predicate out of restricted predicate range
64 bic z0.d, p8/z, z0.d, z1.d
65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
66 // CHECK-NEXT: bic z0.d, p8/z, z0.d, z1.d
67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
70 // --------------------------------------------------------------------------//
71 // Predicate register must have .b suffix
73 bic p0.h, p0/z, p0.h, p1.h
74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
75 // CHECK-NEXT: bic p0.h, p0/z, p0.h, p1.h
76 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
78 bic p0.s, p0/z, p0.s, p1.s
79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
80 // CHECK-NEXT: bic p0.s, p0/z, p0.s, p1.s
81 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
83 bic p0.d, p0/z, p0.d, p1.d
84 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
85 // CHECK-NEXT: bic p0.d, p0/z, p0.d, p1.d
86 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
88 // --------------------------------------------------------------------------//
89 // Operation only has zeroing predicate behaviour (p0/z).
91 bic p0.b, p0/m, p1.b, p2.b
92 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
93 // CHECK-NEXT: bic p0.b, p0/m, p1.b, p2.b
94 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
97 // --------------------------------------------------------------------------//
98 // Negative tests for instructions that are incompatible with movprfx
100 movprfx z0.d, p0/z, z7.d
101 bic z0.d, z0.d, #0x6
102 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
103 // CHECK-NEXT: bic z0.d, z0.d, #0x6
104 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
106 movprfx z23.d, p0/z, z30.d
107 bic z23.d, z13.d, z8.d
108 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
109 // CHECK-NEXT: bic z23.d, z13.d, z8.d
110 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
112 movprfx z23, z30
113 bic z23.d, z13.d, z8.d
114 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
115 // CHECK-NEXT: bic z23.d, z13.d, z8.d
116 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: